mirror of
https://github.com/EFeru/hoverboard-sideboard-hack-GD.git
synced 2025-08-18 01:26:11 +00:00
iBUS on AUX Serial is working
- implemented iBUS - updated the Tabs to spaces
This commit is contained in:
EmanuelFeru
428
Src/i2c_it.c
428
Src/i2c_it.c
@@ -47,117 +47,117 @@ extern volatile int8_t i2c_aux_nRABytes;
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void I2C0_EventIRQ_Handler(void)
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{
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uint16_t k;
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if (i2c_ReadWriteCmd == WRITE) { // check for WRITE command
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// ======================================== WRITE ========================================
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// --------------------------------------------------------------------
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// | Master | S | AD+W | | RA | | DATA | | DATA | | P |
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// | Slave | | | ACK | | ACK | | ACK | | ACK | |
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// --------------------------------------------------------------------
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if (i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_SBSEND)) { // check if start condition is sent out in master mode
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i2c_master_addressing(I2C0, i2c_slaveAddress, I2C_TRANSMITTER); // send slave address with Transmit request
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} else if (i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_ADDSEND)) { // check if address is sent in master mode
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i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_ADDSEND); // clear ADDSEND bit
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} else if (i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_TBE)) { // check if I2C_DATA is empty (Transmitted Byte Empty)
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if (i2c_nRABytes > 0) { // check if the Register Address has been sent
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i2c_data_transmit(I2C0, i2c_regAddress); // the master sends the Register Address byte
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i2c_nRABytes--;
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} else {
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if (i2c_nDABytes > 0) {
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i2c_data_transmit(I2C0, *i2c_txbuffer++); // the master sends a data byte
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i2c_nDABytes--;
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if (0 == i2c_nDABytes) {
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i2c_status = 0; // 0 = Success
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}
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for(k=0; k<500; k++) {
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#ifdef __GNUC__
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asm volatile ("nop"); // unoptimizable NOP loop, 500 times to make some clock cycles delay (otherwise DMP writing will fail!! Reason unknown yet.. could be that writing to MPU6050 memory takes a bit more time)
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#else
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__asm volatile ("nop");
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#endif
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}
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} else {
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i2c_stop_on_bus(I2C0); // the master sends a stop condition to I2C bus
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i2c_interrupt_disable(I2C0, I2C_INT_ERR | I2C_INT_BUF | I2C_INT_EV); // disable the I2C0 interrupt
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}
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}
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}
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} else if (i2c_ReadWriteCmd == READ) { // check for READ command
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uint16_t k;
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if (i2c_ReadWriteCmd == WRITE) { // check for WRITE command
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// ======================================== READ ========================================
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// --------------------------------------------------------------------------------------
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// | Master | S | AD+W | | RA | | S | AD+R | | ACK | | NACK | P |
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// | Slave | | | ACK | | ACK | | | ACK | DATA | | DATA | | |
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// --------------------------------------------------------------------------------------
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// <---------- Phase 1 ----------> <---------------- Phase 2 ---------------->
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// Phase 1 - send the Register Address
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if (i2c_nRABytes >= 0) {
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if (i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_SBSEND)) { // check if start condition is sent out in master mode
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i2c_master_addressing(I2C0, i2c_slaveAddress, I2C_TRANSMITTER); // send slave address with Transmit request
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} else if (i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_ADDSEND)) { // check if address is sent in master mode
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i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_ADDSEND); // clear ADDSEND bit
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} else if (i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_TBE)) { // check if I2C_DATA is empty (Transmitted Byte Empty)
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if (i2c_nRABytes > 0) { // check RABytes
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i2c_data_transmit(I2C0, i2c_regAddress); // the master sends the Register Address byte
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} else {
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i2c_start_on_bus(I2C0); // send start condition
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}
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i2c_nRABytes--;
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}
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// ======================================== WRITE ========================================
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// --------------------------------------------------------------------
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// | Master | S | AD+W | | RA | | DATA | | DATA | | P |
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// | Slave | | | ACK | | ACK | | ACK | | ACK | |
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// --------------------------------------------------------------------
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// Phase 2 - read Data
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} else {
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if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_SBSEND)){ // check if start condition is sent out in master mode
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i2c_master_addressing(I2C0, i2c_slaveAddress, I2C_RECEIVER); // sends slave address with Receive Request
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}else if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_ADDSEND)){ // check if address is sent in master mode
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if((1 == i2c_nDABytes) || (2 == i2c_nDABytes)){
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i2c_ack_config(I2C0, I2C_ACK_DISABLE); // clear the ACKEN before the ADDSEND is cleared
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i2c_interrupt_flag_clear(I2C0,I2C_INT_FLAG_ADDSEND); // clear the ADDSEND bit
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}else{
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i2c_interrupt_flag_clear(I2C0,I2C_INT_FLAG_ADDSEND); // clear the ADDSEND bit
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}
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}else if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_RBNE)){ // check if I2C_DATA is not Empty (Received Byte Not Empty)
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if(i2c_nDABytes > 0){
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if(3 == i2c_nDABytes){
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while(!i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_BTC)); // wait until the second last data byte is received into the shift register
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i2c_ack_config(I2C0, I2C_ACK_DISABLE); // send a NACK for the last data byte
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}
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*i2c_rxbuffer++ = i2c_data_receive(I2C0); // read a data byte from I2C_DATA
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i2c_nDABytes--;
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if(0 == i2c_nDABytes){
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i2c_stop_on_bus(I2C0); // send a stop condition
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i2c_status = 0; // 0 = Success
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i2c_ack_config(I2C0, I2C_ACK_ENABLE);
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i2c_ackpos_config(I2C0, I2C_ACKPOS_CURRENT);
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i2c_interrupt_disable(I2C0, I2C_INT_ERR | I2C_INT_BUF | I2C_INT_EV);
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}
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}
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}
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if (i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_SBSEND)) { // check if start condition is sent out in master mode
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i2c_master_addressing(I2C0, i2c_slaveAddress, I2C_TRANSMITTER); // send slave address with Transmit request
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} else if (i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_ADDSEND)) { // check if address is sent in master mode
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i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_ADDSEND); // clear ADDSEND bit
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} else if (i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_TBE)) { // check if I2C_DATA is empty (Transmitted Byte Empty)
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if (i2c_nRABytes > 0) { // check if the Register Address has been sent
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i2c_data_transmit(I2C0, i2c_regAddress); // the master sends the Register Address byte
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i2c_nRABytes--;
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} else {
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if (i2c_nDABytes > 0) {
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i2c_data_transmit(I2C0, *i2c_txbuffer++); // the master sends a data byte
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i2c_nDABytes--;
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if (0 == i2c_nDABytes) {
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i2c_status = 0; // 0 = Success
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}
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for(k=0; k<500; k++) {
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#ifdef __GNUC__
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asm volatile ("nop"); // unoptimizable NOP loop, 500 times to make some clock cycles delay (otherwise DMP writing will fail!! Reason unknown yet.. could be that writing to MPU6050 memory takes a bit more time)
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#else
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__asm volatile ("nop");
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#endif
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}
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} else {
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i2c_stop_on_bus(I2C0); // the master sends a stop condition to I2C bus
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i2c_interrupt_disable(I2C0, I2C_INT_ERR | I2C_INT_BUF | I2C_INT_EV); // disable the I2C0 interrupt
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}
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}
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}
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} else if (i2c_ReadWriteCmd == READ) { // check for READ command
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// ======================================== READ ========================================
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// --------------------------------------------------------------------------------------
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// | Master | S | AD+W | | RA | | S | AD+R | | ACK | | NACK | P |
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// | Slave | | | ACK | | ACK | | | ACK | DATA | | DATA | | |
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// --------------------------------------------------------------------------------------
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// <---------- Phase 1 ----------> <---------------- Phase 2 ---------------->
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// Phase 1 - send the Register Address
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if (i2c_nRABytes >= 0) {
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if (i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_SBSEND)) { // check if start condition is sent out in master mode
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i2c_master_addressing(I2C0, i2c_slaveAddress, I2C_TRANSMITTER); // send slave address with Transmit request
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} else if (i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_ADDSEND)) { // check if address is sent in master mode
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i2c_interrupt_flag_clear(I2C0, I2C_INT_FLAG_ADDSEND); // clear ADDSEND bit
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} else if (i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_TBE)) { // check if I2C_DATA is empty (Transmitted Byte Empty)
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if (i2c_nRABytes > 0) { // check RABytes
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i2c_data_transmit(I2C0, i2c_regAddress); // the master sends the Register Address byte
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} else {
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i2c_start_on_bus(I2C0); // send start condition
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}
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i2c_nRABytes--;
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}
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// Phase 2 - read Data
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} else {
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if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_SBSEND)){ // check if start condition is sent out in master mode
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i2c_master_addressing(I2C0, i2c_slaveAddress, I2C_RECEIVER); // sends slave address with Receive Request
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}else if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_ADDSEND)){ // check if address is sent in master mode
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if((1 == i2c_nDABytes) || (2 == i2c_nDABytes)){
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i2c_ack_config(I2C0, I2C_ACK_DISABLE); // clear the ACKEN before the ADDSEND is cleared
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i2c_interrupt_flag_clear(I2C0,I2C_INT_FLAG_ADDSEND); // clear the ADDSEND bit
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}else{
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i2c_interrupt_flag_clear(I2C0,I2C_INT_FLAG_ADDSEND); // clear the ADDSEND bit
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}
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}else if(i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_RBNE)){ // check if I2C_DATA is not Empty (Received Byte Not Empty)
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if(i2c_nDABytes > 0){
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if(3 == i2c_nDABytes){
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while(!i2c_interrupt_flag_get(I2C0, I2C_INT_FLAG_BTC)); // wait until the second last data byte is received into the shift register
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i2c_ack_config(I2C0, I2C_ACK_DISABLE); // send a NACK for the last data byte
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}
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*i2c_rxbuffer++ = i2c_data_receive(I2C0); // read a data byte from I2C_DATA
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i2c_nDABytes--;
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if(0 == i2c_nDABytes) {
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i2c_stop_on_bus(I2C0); // send a stop condition
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i2c_status = 0; // 0 = Success
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i2c_ack_config(I2C0, I2C_ACK_ENABLE);
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i2c_ackpos_config(I2C0, I2C_ACKPOS_CURRENT);
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i2c_interrupt_disable(I2C0, I2C_INT_ERR | I2C_INT_BUF | I2C_INT_EV);
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}
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}
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}
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}
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}
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}
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}
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}
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@@ -212,115 +212,115 @@ void I2C0_ErrorIRQ_Handler(void)
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*/
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void I2C1_EventIRQ_Handler(void)
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{
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uint16_t k;
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if (i2c_aux_ReadWriteCmd == WRITE) { // check for WRITE command
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// ======================================== WRITE ========================================
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// --------------------------------------------------------------------
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// | Master | S | AD+W | | RA | | DATA | | DATA | | P |
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// | Slave | | | ACK | | ACK | | ACK | | ACK | |
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// --------------------------------------------------------------------
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if (i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_SBSEND)) { // check if start condition is sent out in master mode
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i2c_master_addressing(I2C1, i2c_aux_slaveAddress, I2C_TRANSMITTER); // send slave address with Transmit request
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} else if (i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_ADDSEND)) { // check if address is sent in master mode
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i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_ADDSEND); // clear ADDSEND bit
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} else if (i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_TBE)) { // check if I2C_DATA is empty (Transmitted Byte Empty)
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if (i2c_aux_nRABytes > 0) { // check if the Register Address has been sent
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i2c_data_transmit(I2C1, i2c_aux_regAddress); // the master sends the Register Address byte
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i2c_aux_nRABytes--;
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} else {
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if (i2c_aux_nDABytes > 0) {
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i2c_data_transmit(I2C1, *i2c_aux_txbuffer++); // the master sends a data byte
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i2c_aux_nDABytes--;
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for(k=0; k<500; k++);
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if (0 == i2c_aux_nDABytes) {
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i2c_aux_status = 0; // 0 = Success
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}
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#ifdef __GNUC__
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asm volatile ("nop"); // unoptimizable NOP loop, 500 times to make some clock cycles delay (otherwise DMP writing will fail!! Reason unknown yet.. could be that writing to MPU6050 memory takes a bit more time)
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#else
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__asm volatile ("nop");
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#endif
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} else {
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i2c_stop_on_bus(I2C1); // the master sends a stop condition to I2C bus
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i2c_interrupt_disable(I2C1, I2C_INT_ERR | I2C_INT_BUF | I2C_INT_EV); // disable the I2C0 interrupt
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}
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}
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}
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} else if (i2c_aux_ReadWriteCmd == READ) { // check for READ command
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uint16_t k;
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if (i2c_aux_ReadWriteCmd == WRITE) { // check for WRITE command
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// ======================================== WRITE ========================================
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// --------------------------------------------------------------------
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// | Master | S | AD+W | | RA | | DATA | | DATA | | P |
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// | Slave | | | ACK | | ACK | | ACK | | ACK | |
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// --------------------------------------------------------------------
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// ======================================== READ ========================================
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// --------------------------------------------------------------------------------------
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// | Master | S | AD+W | | RA | | S | AD+R | | ACK | | NACK | P |
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// | Slave | | | ACK | | ACK | | | ACK | DATA | | DATA | | |
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// --------------------------------------------------------------------------------------
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// <---------- Phase 1 ----------> <---------------- Phase 2 ---------------->
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// Phase 1 - send the Register Address
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if (i2c_aux_nRABytes >= 0) {
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if (i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_SBSEND)) { // check if start condition is sent out in master mode
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i2c_master_addressing(I2C1, i2c_aux_slaveAddress, I2C_TRANSMITTER); // send slave address with Transmit request
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} else if (i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_ADDSEND)) { // check if address is sent in master mode
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i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_ADDSEND); // clear ADDSEND bit
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} else if (i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_TBE)) { // check if I2C_DATA is empty (Transmitted Byte Empty)
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if (i2c_aux_nRABytes > 0) { // check RABytes
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i2c_data_transmit(I2C1, i2c_aux_regAddress); // the master sends the Register Address byte
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} else {
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i2c_start_on_bus(I2C1); // send start condition
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}
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i2c_aux_nRABytes--;
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}
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if (i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_SBSEND)) { // check if start condition is sent out in master mode
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// Phase 2 - read Data
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} else {
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if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_SBSEND)){ // check if start condition is sent out in master mode
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i2c_master_addressing(I2C1, i2c_aux_slaveAddress, I2C_RECEIVER); // sends slave address with Receive Request
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}else if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_ADDSEND)){ // check if address is sent in master mode
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if((1 == i2c_aux_nDABytes) || (2 == i2c_aux_nDABytes)){
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i2c_ack_config(I2C1, I2C_ACK_DISABLE); // clear the ACKEN before the ADDSEND is cleared
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i2c_interrupt_flag_clear(I2C1,I2C_INT_FLAG_ADDSEND); // clear the ADDSEND bit
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}else{
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i2c_interrupt_flag_clear(I2C1,I2C_INT_FLAG_ADDSEND); // clear the ADDSEND bit
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}
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}else if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_RBNE)){ // check if I2C_DATA is not Empty (Received Byte Not Empty)
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if(i2c_aux_nDABytes > 0){
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if(3 == i2c_aux_nDABytes){
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while(!i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_BTC)); // wait until the second last data byte is received into the shift register
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i2c_ack_config(I2C1, I2C_ACK_DISABLE); // send a NACK for the last data byte
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}
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*i2c_aux_rxbuffer++ = i2c_data_receive(I2C1); // read a data byte from I2C_DATA
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i2c_aux_nDABytes--;
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if(0 == i2c_aux_nDABytes){
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i2c_stop_on_bus(I2C1); // send a stop condition
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i2c_aux_status = 0; // 0 = Success
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i2c_ack_config(I2C1, I2C_ACK_ENABLE);
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i2c_ackpos_config(I2C1, I2C_ACKPOS_CURRENT);
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i2c_interrupt_disable(I2C1, I2C_INT_ERR | I2C_INT_BUF | I2C_INT_EV);
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}
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}
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}
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i2c_master_addressing(I2C1, i2c_aux_slaveAddress, I2C_TRANSMITTER); // send slave address with Transmit request
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}
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}
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} else if (i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_ADDSEND)) { // check if address is sent in master mode
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||||
i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_ADDSEND); // clear ADDSEND bit
|
||||
|
||||
} else if (i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_TBE)) { // check if I2C_DATA is empty (Transmitted Byte Empty)
|
||||
|
||||
if (i2c_aux_nRABytes > 0) { // check if the Register Address has been sent
|
||||
i2c_data_transmit(I2C1, i2c_aux_regAddress); // the master sends the Register Address byte
|
||||
i2c_aux_nRABytes--;
|
||||
} else {
|
||||
if (i2c_aux_nDABytes > 0) {
|
||||
i2c_data_transmit(I2C1, *i2c_aux_txbuffer++); // the master sends a data byte
|
||||
i2c_aux_nDABytes--;
|
||||
for(k=0; k<500; k++);
|
||||
if (0 == i2c_aux_nDABytes) {
|
||||
i2c_aux_status = 0; // 0 = Success
|
||||
}
|
||||
#ifdef __GNUC__
|
||||
asm volatile ("nop"); // unoptimizable NOP loop, 500 times to make some clock cycles delay (otherwise DMP writing will fail!! Reason unknown yet.. could be that writing to MPU6050 memory takes a bit more time)
|
||||
#else
|
||||
__asm volatile ("nop");
|
||||
#endif
|
||||
} else {
|
||||
i2c_stop_on_bus(I2C1); // the master sends a stop condition to I2C bus
|
||||
i2c_interrupt_disable(I2C1, I2C_INT_ERR | I2C_INT_BUF | I2C_INT_EV); // disable the I2C0 interrupt
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
} else if (i2c_aux_ReadWriteCmd == READ) { // check for READ command
|
||||
|
||||
// ======================================== READ ========================================
|
||||
// --------------------------------------------------------------------------------------
|
||||
// | Master | S | AD+W | | RA | | S | AD+R | | ACK | | NACK | P |
|
||||
// | Slave | | | ACK | | ACK | | | ACK | DATA | | DATA | | |
|
||||
// --------------------------------------------------------------------------------------
|
||||
// <---------- Phase 1 ----------> <---------------- Phase 2 ---------------->
|
||||
|
||||
// Phase 1 - send the Register Address
|
||||
if (i2c_aux_nRABytes >= 0) {
|
||||
|
||||
if (i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_SBSEND)) { // check if start condition is sent out in master mode
|
||||
|
||||
i2c_master_addressing(I2C1, i2c_aux_slaveAddress, I2C_TRANSMITTER); // send slave address with Transmit request
|
||||
|
||||
} else if (i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_ADDSEND)) { // check if address is sent in master mode
|
||||
|
||||
i2c_interrupt_flag_clear(I2C1, I2C_INT_FLAG_ADDSEND); // clear ADDSEND bit
|
||||
|
||||
} else if (i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_TBE)) { // check if I2C_DATA is empty (Transmitted Byte Empty)
|
||||
if (i2c_aux_nRABytes > 0) { // check RABytes
|
||||
i2c_data_transmit(I2C1, i2c_aux_regAddress); // the master sends the Register Address byte
|
||||
} else {
|
||||
i2c_start_on_bus(I2C1); // send start condition
|
||||
}
|
||||
i2c_aux_nRABytes--;
|
||||
}
|
||||
|
||||
// Phase 2 - read Data
|
||||
} else {
|
||||
|
||||
if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_SBSEND)){ // check if start condition is sent out in master mode
|
||||
|
||||
i2c_master_addressing(I2C1, i2c_aux_slaveAddress, I2C_RECEIVER); // sends slave address with Receive Request
|
||||
|
||||
}else if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_ADDSEND)){ // check if address is sent in master mode
|
||||
|
||||
if((1 == i2c_aux_nDABytes) || (2 == i2c_aux_nDABytes)){
|
||||
i2c_ack_config(I2C1, I2C_ACK_DISABLE); // clear the ACKEN before the ADDSEND is cleared
|
||||
i2c_interrupt_flag_clear(I2C1,I2C_INT_FLAG_ADDSEND); // clear the ADDSEND bit
|
||||
}else{
|
||||
i2c_interrupt_flag_clear(I2C1,I2C_INT_FLAG_ADDSEND); // clear the ADDSEND bit
|
||||
}
|
||||
|
||||
}else if(i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_RBNE)){ // check if I2C_DATA is not Empty (Received Byte Not Empty)
|
||||
if(i2c_aux_nDABytes > 0){
|
||||
if(3 == i2c_aux_nDABytes){
|
||||
while(!i2c_interrupt_flag_get(I2C1, I2C_INT_FLAG_BTC)); // wait until the second last data byte is received into the shift register
|
||||
i2c_ack_config(I2C1, I2C_ACK_DISABLE); // send a NACK for the last data byte
|
||||
}
|
||||
*i2c_aux_rxbuffer++ = i2c_data_receive(I2C1); // read a data byte from I2C_DATA
|
||||
i2c_aux_nDABytes--;
|
||||
if(0 == i2c_aux_nDABytes){
|
||||
i2c_stop_on_bus(I2C1); // send a stop condition
|
||||
i2c_aux_status = 0; // 0 = Success
|
||||
i2c_ack_config(I2C1, I2C_ACK_ENABLE);
|
||||
i2c_ackpos_config(I2C1, I2C_ACKPOS_CURRENT);
|
||||
i2c_interrupt_disable(I2C1, I2C_INT_ERR | I2C_INT_BUF | I2C_INT_EV);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
|
||||
Reference in New Issue
Block a user