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Initial commit
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EmanuelFeru
333
Drivers/CMSIS/Source/system_gd32f1x0.c
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333
Drivers/CMSIS/Source/system_gd32f1x0.c
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/*!
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\file system_gd32f1x0.c
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\brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for
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GD32F1x0 Device Series
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*/
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/* Copyright (c) 2012 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
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#include "gd32f1x0.h"
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/* system frequency define */
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#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
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#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
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#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
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/* select a system clock by uncommenting the following line */
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//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL)
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//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M)
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//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
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#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000)
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#define SEL_IRC8M 0x00
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#define SEL_HXTAL 0x01
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#define SEL_PLL 0x02
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/* set the system clock frequency and declare the system clock configuration function */
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#ifdef __SYSTEM_CLOCK_8M_HXTAL
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL;
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static void system_clock_8m_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
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static void system_clock_72m_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2;
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static void system_clock_72m_irc8m(void);
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#else
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M;
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static void system_clock_8m_irc8m(void);
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#endif /* __SYSTEM_CLOCK_8M_HXTAL */
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/* configure the system clock */
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static void system_clock_config(void);
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/*!
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\brief setup the microcontroller system, initialize the system
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\param[in] none
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\param[out] none
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\retval none
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*/
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void SystemInit (void)
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{
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/* enable IRC8M */
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RCU_CTL0 |= RCU_CTL0_IRC8MEN;
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while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
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}
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/* reset RCU */
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#ifdef GD32F130_150
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RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
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RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
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#elif defined (GD32F170_190)
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RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
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RCU_CFG0_ADCPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV | RCU_CFG0_PLLDV);
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#endif /* GD32F130_150 */
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RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
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#ifdef GD32F130_150
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RCU_CFG0 &= ~(RCU_CFG0_USBDPSC);
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#endif /* GD32F130_150 */
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RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
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RCU_CFG1 &= ~RCU_CFG1_HXTALPREDV;
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RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_CECSEL | RCU_CFG2_ADCSEL);
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#ifdef GD32F130_150
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RCU_CTL1 &= ~RCU_CTL1_IRC14MEN;
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#elif defined (GD32F170_190)
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RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
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RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
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RCU_CFG3 &= ~RCU_CFG3_CKOUT1SRC;
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RCU_CFG3 &= ~RCU_CFG3_CKOUT1DIV;
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#endif /* GD32F130_150 */
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RCU_INT = 0x00000000U;
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/* configure system clock */
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system_clock_config();
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}
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/*!
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\brief configure the system clock
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_config(void)
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{
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#ifdef __SYSTEM_CLOCK_8M_HXTAL
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system_clock_8m_hxtal();
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#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
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system_clock_72m_hxtal();
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#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
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system_clock_72m_irc8m();
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#else
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system_clock_8m_irc8m();
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#endif /* __SYSTEM_CLOCK_8M_HXTAL */
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}
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#ifdef __SYSTEM_CLOCK_8M_HXTAL
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/*!
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\brief configure the system clock to 8M by HXTAL
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_8m_hxtal(void)
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{
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uint32_t timeout = 0;
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/* enable HXTAL */
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RCU_CTL0 |= RCU_CTL0_HXTALEN;
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/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
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while((0 == (RCU_CTL0 & RCU_CTL0_HXTALSTB)) && (HXTAL_STARTUP_TIMEOUT != timeout++));
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/* if fail */
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if(0 == (RCU_CTL0 & RCU_CTL0_HXTALSTB))
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return;
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/* HXTAL is stable */
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/* AHB = SYSCLK */
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RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
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/* APB2 = AHB */
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RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
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/* APB1 = AHB */
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RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
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/* select HXTAL as system clock */
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RCU_CFG0 &= ~RCU_CFG0_SCS;
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RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
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/* wait until HXTAL is selected as system clock */
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while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL));
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}
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#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
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/*!
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\brief configure the system clock to 72M by PLL which selects HXTAL as its clock source
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_72m_hxtal(void)
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{
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uint32_t timeout = 0U;
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uint32_t stab_flag = 0U;
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/* enable HXTAL */
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RCU_CTL0 |= RCU_CTL0_HXTALEN;
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/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
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do{
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timeout++;
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stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
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}
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while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
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/* if fail */
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if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
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return;
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}
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/* HXTAL is stable */
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/* AHB = SYSCLK */
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RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
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/* APB2 = AHB */
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RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
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/* APB1 = AHB */
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RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
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/* PLL = HXTAL * 9 = 72 MHz */
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RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
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RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9);
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/* enable PLL */
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RCU_CTL0 |= RCU_CTL0_PLLEN;
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/* wait until PLL is stable */
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while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
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}
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/* select PLL as system clock */
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RCU_CFG0 &= ~RCU_CFG0_SCS;
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RCU_CFG0 |= RCU_CKSYSSRC_PLL;
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/* wait until PLL is selected as system clock */
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while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
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}
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}
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#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
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/*!
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\brief configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_72m_irc8m(void)
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{
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/* AHB = SYSCLK */
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RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
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/* APB2 = AHB */
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RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
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/* APB1 = AHB */
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RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
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/* PLL = (IRC8M/2) * 18 = 72 MHz */
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RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
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RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);
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/* enable PLL */
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RCU_CTL0 |= RCU_CTL0_PLLEN;
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/* wait until PLL is stable */
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while(0 == (RCU_CTL0 & RCU_CTL0_PLLSTB));
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/* select PLL as system clock */
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RCU_CFG0 &= ~RCU_CFG0_SCS;
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RCU_CFG0 |= RCU_CKSYSSRC_PLL;
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/* wait until PLL is selected as system clock */
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while(0 == (RCU_CFG0 & RCU_SCSS_PLL));
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}
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#else
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/*!
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\brief configure the system clock to 8M by IRC8M
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_8m_irc8m(void)
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{
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/* AHB = SYSCLK */
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RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
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/* APB2 = AHB */
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RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
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/* APB1 = AHB */
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RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
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/* select IRC8M as system clock */
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RCU_CFG0 &= ~RCU_CFG0_SCS;
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RCU_CFG0 |= RCU_CKSYSSRC_IRC8M;
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/* wait until IRC8M is selected as system clock */
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while(0 != (RCU_CFG0 & RCU_SCSS_IRC8M));
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}
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#endif /* __SYSTEM_CLOCK_8M_HXTAL */
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/*!
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\brief update the SystemCoreClock with current core clock retrieved from cpu registers
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\param[in] none
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\param[out] none
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\retval none
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t sws = 0U;
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uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
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/* exponent of AHB clock divider */
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const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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sws = GET_BITS(RCU_CFG0, 2, 3);
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switch(sws){
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/* IRC8M is selected as CK_SYS */
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case SEL_IRC8M:
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SystemCoreClock = IRC8M_VALUE;
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break;
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/* HXTAL is selected as CK_SYS */
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case SEL_HXTAL:
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SystemCoreClock = HXTAL_VALUE;
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break;
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/* PLL is selected as CK_SYS */
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case SEL_PLL:
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/* get the value of PLLMF[3:0] */
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pllmf = GET_BITS(RCU_CFG0, 18, 21);
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pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
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/* high 16 bits */
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if(1U == pllmf4){
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pllmf += 17U;
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}else{
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pllmf += 2U;
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}
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/* PLL clock source selection, HXTAL or IRC8M/2 */
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pllsel = GET_BITS(RCU_CFG0, 16, 16);
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if(0U != pllsel){
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prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U);
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SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf;
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}else{
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SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf;
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}
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break;
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/* IRC8M is selected as CK_SYS */
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default:
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SystemCoreClock = IRC8M_VALUE;
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break;
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}
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/* calculate AHB clock frequency */
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idx = GET_BITS(RCU_CFG0, 4, 7);
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clk_exp = ahb_exp[idx];
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SystemCoreClock >>= clk_exp;
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}
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