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EmanuelFeru
2020-02-07 14:57:44 +01:00
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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_adc.h Normal file
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/*!
\file gd32f1x0_adc.h
\brief definitions for the ADC
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_ADC_H
#define GD32F1X0_ADC_H
#include "gd32f1x0.h"
/* ADC definitions */
#define ADC ADC_BASE
/* registers definitions */
#define ADC_STAT REG32(ADC + 0x00U) /*!< ADC status register */
#define ADC_CTL0 REG32(ADC + 0x04U) /*!< ADC control register 0 */
#define ADC_CTL1 REG32(ADC + 0x08U) /*!< ADC control register 1 */
#define ADC_SAMPT0 REG32(ADC + 0x0CU) /*!< ADC sampling time register 0 */
#define ADC_SAMPT1 REG32(ADC + 0x10U) /*!< ADC sampling time register 1 */
#define ADC_IOFF0 REG32(ADC + 0x14U) /*!< ADC inserted channel data offset register 0 */
#define ADC_IOFF1 REG32(ADC + 0x18U) /*!< ADC inserted channel data offset register 1 */
#define ADC_IOFF2 REG32(ADC + 0x1CU) /*!< ADC inserted channel data offset register 2 */
#define ADC_IOFF3 REG32(ADC + 0x20U) /*!< ADC inserted channel data offset register 3 */
#define ADC_WDHT REG32(ADC + 0x24U) /*!< ADC watchdog high threshold register */
#define ADC_WDLT REG32(ADC + 0x28U) /*!< ADC watchdog low threshold register */
#define ADC_RSQ0 REG32(ADC + 0x2CU) /*!< ADC regular sequence register 0 */
#define ADC_RSQ1 REG32(ADC + 0x30U) /*!< ADC regular sequence register 1 */
#define ADC_RSQ2 REG32(ADC + 0x34U) /*!< ADC regular sequence register 2 */
#define ADC_ISQ REG32(ADC + 0x38U) /*!< ADC inserted sequence register */
#define ADC_IDATA0 REG32(ADC + 0x3CU) /*!< ADC inserted data register 0 */
#define ADC_IDATA1 REG32(ADC + 0x40U) /*!< ADC inserted data register 1 */
#define ADC_IDATA2 REG32(ADC + 0x44U) /*!< ADC inserted data register 2 */
#define ADC_IDATA3 REG32(ADC + 0x48U) /*!< ADC inserted data register 3 */
#define ADC_RDATA REG32(ADC + 0x4CU) /*!< ADC regular data register */
#ifdef GD32F170_190
#define ADC_OVSAMPCTL REG32(ADC + 0x80U) /*!< ADC oversampling control register */
#endif /* GD32F170_190 */
/* bits definitions */
/* ADC_STAT */
#define ADC_STAT_WDE BIT(0) /*!< analog watchdog flag */
#define ADC_STAT_EOC BIT(1) /*!< end of conversion */
#define ADC_STAT_EOIC BIT(2) /*!< injected channel end of conversion */
#define ADC_STAT_STIC BIT(3) /*!< injected channel start flag */
#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
/* ADC_CTL0 */
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for injected channels */
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
#define ADC_CTL0_WDSC BIT(9) /*!< enable the watchdog on a single channel in scan mode */
#define ADC_CTL0_ICA BIT(10) /*!< automatic injected group conversion */
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on injected channels */
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
#define ADC_CTL0_IWDEN BIT(22) /*!< inserted channel analog watchdog enable */
#define ADC_CTL0_RWDEN BIT(23) /*!< regular channel analog watchdog enable */
#ifdef GD32F170_190
#define ADC_CTL0_DRES BITS(24,25) /*!< ADC resolution */
#endif /* GD32F170_190 */
/* ADC_CTL1 */
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter ON */
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
#define ADC_CTL1_ETSIC BITS(12,14) /*!< external event select for injected group */
#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger conversion mode for injected channels */
#define ADC_CTL1_ETSRC BITS(17,19) /*!< external event select for regular group */
#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for regular channels */
#define ADC_CTL1_SWICST BIT(21) /*!< start conversion of injected channels */
#define ADC_CTL1_SWRCST BIT(22) /*!< start conversion of regular channels */
#define ADC_CTL1_TSVREN BIT(23) /*!< temperature sensor and VREFINT enable */
#define ADC_CTL1_VBETEN BIT(24) /*!< VBAT enable */
/* ADC_SAMPTx x=0..1 */
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */
/* ADC_IOFFx x=0..3 */
#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for injected channel x */
/* ADC_WHT */
#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
/* ADC_WLT */
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
/* ADC_RSQx */
#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */
#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */
/* ADC_ISQ */
#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */
#define ADC_ISQ_IL BITS(20,21) /*!< injected sequence length */
/* ADC_IDTx x=0..3*/
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< injected data x */
/* ADC_RDT */
#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */
#ifdef GD32F170_190
/* ADC_OVCTL */
#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */
#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */
#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */
#endif /* GD32F170_190 */
/* constants definitions */
/* ADC channel group definitions */
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc injected channel group */
#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and injected channel group */
/* ADC inserted channel definitions */
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc injected channel 0 */
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc injected channel 1 */
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc injected channel 2 */
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc injected channel 3 */
/* ADC special function definitions */
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
/* ADC channel definitions */
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC Channel 0 */
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC Channel 1 */
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC Channel 2 */
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC Channel 3 */
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC Channel 4 */
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC Channel 5 */
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC Channel 6 */
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC Channel 7 */
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC Channel 8 */
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC Channel 9 */
#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC Channel 10 */
#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC Channel 11 */
#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC Channel 12 */
#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC Channel 13 */
#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC Channel 14 */
#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC Channel 15 */
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC Channel 16 */
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC Channel 17 */
#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC Channel 18 */
/* ADC channel sample time */
#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */
#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */
#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */
#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */
#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */
#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */
#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */
#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */
/* ADC data alignment */
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00U) /*!< LSB alignment */
#define ADC_DATAALIGN_LEFT ((uint32_t)0x01U) /*!< MSB alignment */
/* ADC status flag */
#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog flag */
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< injected channel end of conversion */
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< injected channel start flag */
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */
/* ADC interrupt flag */
#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog interrupt */
#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
/* ADC interrupt flag */
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */
/* ADC resolution definitions */
#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24))
#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */
#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */
#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */
#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */
/* ADC external trigger select for regular channel */
#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< external trigger timer 0 CH0 event select for regular channel */
#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< external trigger timer 0 CH1 event select for regular channel */
#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< external trigger timer 0 CH2 event select for regular channel */
#define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< external trigger timer 1 CH1 event select for regular channel */
#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< external trigger timer 2 TRGO event select for regular channel */
#define ADC_EXTTRIG_REGULAR_T14_CH0 CTL1_ETSRC(5) /*!< external trigger timer 14 CH0 event select for regular channel */
#define ADC_EXTTRIG_REGULAR_EXT_IT11 CTL1_ETSRC(6) /*!< external trigger extiline 11 select for regular channel */
#define ADC_EXTTRIG_REGULAR_SWRCST CTL1_ETSRC(7) /*!< software trigger select for regular channel */
/* ADC external trigger select for inserted channel */
#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12))
#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< external trigger timer0 TRGO event select for inserted channel */
#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< external trigger timer0 CH3 event select for inserted channel */
#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< external trigger timer1 TRGO event select for inserted channel */
#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< external trigger timer1 CH0 event select for inserted channel */
#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< external trigger timer2 CH3 event select for inserted channel */
#define ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5) /*!< external trigger timer14 TRGO event select for inserted channel */
#define ADC_EXTTRIG_INSERTED_EXT_IT15 CTL1_ETSIC(6) /*!< external interrupt line 15 select for inserted channel */
#define ADC_EXTTRIG_INSERTED_SWRCST CTL1_ETSIC(7) /*!< software trigger select for inserted channel */
/* adc_ioffx register value */
#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
#ifdef GD32F170_190
/* ADC oversampling mode */
#define ADC_OVERSAMPLING_ALL_CONVERT 0 /*!< all oversampled conversions for a channel are done consecutively after a trigger */
#define ADC_OVERSAMPLING_ONE_CONVERT 1 /*!< each oversampled conversion for a channel needs a trigger */
/* ADC oversampling shift */
#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */
/* ADC oversampling ratio */
#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2))
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio X2 */
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio X4 */
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio X8 */
#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio X16 */
#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio X32 */
#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio X64 */
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio X128 */
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio X256 */
#endif /* GD32F170_190 */
/* function declarations */
/* ADC reset */
void adc_deinit(void);
/* enable ADC interface */
void adc_enable(void);
/* disable ADC interface */
void adc_disable(void);
/* ADC calibration and reset calibration */
void adc_calibration_enable(void);
/* enable DMA request */
void adc_dma_mode_enable(void);
/* disable DMA request */
void adc_dma_mode_disable(void);
/* enable the temperature sensor and Vrefint channel */
void adc_tempsensor_vrefint_enable(void);
/* disable the temperature sensor and Vrefint channel */
void adc_tempsensor_vrefint_disable(void);
/* enable the vbat channel */
void adc_vbat_enable(void);
/* disable the vbat channel */
void adc_vbat_disable(void);
/* ADC discontinuous mode */
void adc_discontinuous_mode_config(uint8_t channel_group,uint8_t length);
/* ADC special function config */
void adc_special_function_config(uint32_t function, ControlStatus newvalue);
/* ADC data alignment config */
void adc_data_alignment_config(uint32_t data_alignment);
/* ADC channel length config */
void adc_channel_length_config(uint8_t channel_group,uint32_t length);
/* ADC regular channel config */
void adc_regular_channel_config(uint8_t rank,uint8_t channel,uint32_t sample_time);
/* ADC inserted channel config */
void adc_inserted_channel_config(uint8_t rank,uint8_t channel,uint32_t sample_time);
/* ADC inserted channel offset config */
void adc_inserted_channel_offset_config(uint8_t inserted_channel,uint16_t offset);
/* ADC external trigger enable */
void adc_external_trigger_config(uint8_t channel_group,ControlStatus newvalue);
/* ADC external trigger source config */
void adc_external_trigger_source_config(uint8_t channel_group,uint32_t external_trigger_source);
/* ADC software trigger enable */
void adc_software_trigger_enable(uint8_t channel_group);
/* ADC regular group data register read */
uint16_t adc_regular_data_read(void);
/* ADC inserted group data register read */
uint16_t adc_inserted_data_read(uint8_t inserted_channel);
/* get the ADC status flag */
FlagStatus adc_flag_get(uint32_t flag);
/* clear the ADC status flag */
void adc_flag_clear(uint32_t flag);
/* get the ADC interrupt flag */
FlagStatus adc_interrupt_flag_get(uint32_t flag);
/* clear the ADC interrupt or status flag */
void adc_interrupt_flag_clear(uint32_t flag);
/* ADC interrupt enable */
void adc_interrupt_enable(uint32_t interrupt);
/* ADC interrupt disable */
void adc_interrupt_disable(uint32_t interrupt);
/* ADC analog watchdog single channel config */
void adc_watchdog_single_channel_enable(uint8_t channel);
/* ADC analog watchdog group channel config */
void adc_watchdog_group_channel_enable(uint8_t channel_group);
/* ADC analog watchdog disable */
void adc_watchdog_disable(void);
/* ADC analog watchdog threshold config */
void adc_watchdog_threshold_config(uint16_t low_threshold,uint16_t high_threshold);
#ifdef GD32F170_190
/* ADC resolution config */
void adc_resolution_config(uint32_t resolution);
/* ADC oversample mode config */
void adc_oversample_mode_config(uint8_t mode,uint16_t shift,uint8_t ratio);
/* enable ADC oversample mode */
void adc_oversample_mode_enable(void);
/* disable ADC oversample mode */
void adc_oversample_mode_disable(void);
#endif /* GD32F170_190 */
#endif /* GD32F1X0_ADC_H */

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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_can.h Normal file
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/*!
\file gd32f1x0_can.h
\brief definitions for the CAN
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifdef GD32F170_190
#ifndef GD32F1X0_CAN_H
#define GD32F1X0_CAN_H
#include "gd32f1x0.h"
/* CAN definitions */
#define CAN0 CAN_BASE /*!< CAN0 base address */
#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */
/* registers definitions */
#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */
#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */
#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/
#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */
#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */
#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */
#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */
#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */
#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */
#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */
#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */
#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */
#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */
#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */
#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */
#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */
#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */
#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */
#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */
#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */
#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */
#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */
#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */
#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO0 mailbox data1 register */
#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */
#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */
#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */
#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */
#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */
#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */
#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */
#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */
#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */
#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */
#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */
#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */
#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */
#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */
#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */
#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */
#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */
#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */
#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */
#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */
#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */
#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */
#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */
#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */
#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */
#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */
#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */
#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */
#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */
#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */
#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */
#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */
#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */
#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */
#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */
#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */
#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */
#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */
#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */
#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */
#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */
#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */
#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */
#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */
#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */
#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */
#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */
#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */
#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */
#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */
#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */
#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */
#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */
#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */
#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */
#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */
#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */
#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */
#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */
#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */
#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */
#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */
#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */
#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */
#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */
#define CAN_PHYCTL(canx) REG32((canx) + 0x3FCU) /*!< CAN PHY control register */
/* CAN transmit mailbox bank */
#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */
#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */
#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */
#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */
/* CAN filter bank */
#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */
#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */
/* CAN receive fifo mailbox bank */
#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */
#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */
#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */
#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */
/* bits definitions */
/* CAN_CTL */
#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */
#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */
#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */
#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */
#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */
#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */
#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */
#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */
#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */
#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */
/* CAN_STAT */
#define CAN_STAT_IWS BIT(0) /*!< initial working state */
#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */
#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/
#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */
#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */
#define CAN_STAT_TS BIT(8) /*!< transmitting state */
#define CAN_STAT_RS BIT(9) /*!< receiving state */
#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */
#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */
/* CAN_TSTAT */
#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */
#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */
#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */
#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */
#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */
#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */
#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */
#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */
#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */
#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */
#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */
#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */
#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */
#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */
#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */
#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */
#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */
#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */
#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */
#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */
#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */
#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */
/* CAN_RFIFO0 */
#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */
#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */
#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */
#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */
/* CAN_RFIFO1 */
#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */
#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */
#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */
#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */
/* CAN_INTEN */
#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */
#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */
#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */
#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */
#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */
#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */
#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */
#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */
#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */
#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */
#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */
#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */
#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */
#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */
/* CAN_ERR */
#define CAN_ERR_WERR BIT(0) /*!< warning error */
#define CAN_ERR_PERR BIT(1) /*!< passive error */
#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */
#define CAN_ERR_ERRN BITS(4,6) /*!< error number */
#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */
#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */
/* CAN_BT */
#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */
#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */
#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */
#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */
#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */
#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */
/* CAN_TMIx */
#define CAN_TMI_TEN BIT(0) /*!< transmit enable */
#define CAN_TMI_FT BIT(1) /*!< frame type */
#define CAN_TMI_FF BIT(2) /*!< frame format */
#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */
#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */
/* CAN_TMPx */
#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */
#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */
#define CAN_TMP_TS BITS(16,31) /*!< time stamp */
/* CAN_TMDATA0x */
#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */
#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */
#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */
#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */
/* CAN_TMDATA1x */
#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */
#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */
#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */
#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */
/* CAN_RFIFOMIx */
#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */
#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */
#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */
#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */
/* CAN_RFIFOMPx */
#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */
#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */
#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */
/* CAN_RFIFOMDATA0x */
#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */
#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */
#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */
#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */
/* CAN_RFIFOMDATA1x */
#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */
#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */
#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */
#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */
/* CAN_FCTL */
#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */
#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */
/* CAN_FMCFG */
#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/
/* CAN_FSCFG */
#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/
/* CAN_FAFIFO */
#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */
/* CAN_FW */
#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */
/* CAN_FxDATAy */
#define CAN_FDATA_FD BITS(0,31) /*!< filter data */
/* CAN_PHYCTL */
#define CAN_PHYCTL_PHYEN BIT(0) /*!< PHY enable */
#define CAN_PHYCTL_POMOD BITS(8,9) /*!< PHY mode */
/* consts definitions */
/* define the CAN bit position and its register index offset */
#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6)))
#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12)))
#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
/* register offset */
#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */
#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */
#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */
#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */
#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */
/* CAN flags */
typedef enum
{
/* flags in TSTAT register */
CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */
CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */
CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */
CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */
CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */
CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */
/* flags in RFIFO0 register */
CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */
CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */
/* flags in RFIFO1 register */
CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */
CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */
/* flags in ERR register */
CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */
CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */
CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */
}can_flag_enum;
/* CAN interrupt flags */
typedef enum
{
/* interrupt flags in STAT register */
CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */
CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */
CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */
/* interrupt flags in TSTAT register */
CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */
CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */
CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */
/* interrupt flags in RFIFO0 register */
CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */
CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */
/* interrupt flags in RFIFO0 register */
CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */
CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */
}can_interrupt_flag_enum;
/* CAN initiliaze parameters struct */
typedef struct
{
uint8_t working_mode; /*!< CAN working mode */
uint8_t resync_jump_width; /*!< CAN resynchronization jump width */
uint8_t time_segment_1; /*!< time segment 1 */
uint8_t time_segment_2; /*!< time segment 2 */
ControlStatus time_triggered; /*!< time triggered communication mode */
ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */
ControlStatus auto_wake_up; /*!< automatic wake-up mode */
ControlStatus auto_retrans; /*!< automatic retransmission mode */
ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */
ControlStatus trans_fifo_order; /*!< transmit FIFO order */
uint16_t prescaler; /*!< baudrate prescaler */
}can_parameter_struct;
/* CAN transmit message struct */
typedef struct
{
uint32_t tx_sfid; /*!< standard format frame identifier */
uint32_t tx_efid; /*!< extended format frame identifier */
uint8_t tx_ff; /*!< format of frame, standard or extended format */
uint8_t tx_ft; /*!< type of frame, data or remote */
uint8_t tx_dlen; /*!< data length */
uint8_t tx_data[8]; /*!< transmit data */
}can_trasnmit_message_struct;
/* CAN receive message struct */
typedef struct
{
uint32_t rx_sfid; /*!< standard format frame identifier */
uint32_t rx_efid; /*!< extended format frame identifier */
uint8_t rx_ff; /*!< format of frame, standard or extended format */
uint8_t rx_ft; /*!< type of frame, data or remote */
uint8_t rx_dlen; /*!< data length */
uint8_t rx_data[8]; /*!< receive data */
uint8_t rx_fi; /*!< filtering index */
} can_receive_message_struct;
/* CAN filter parameters struct */
typedef struct
{
uint16_t filter_list_high; /*!< filter list number high bits*/
uint16_t filter_list_low; /*!< filter list number low bits */
uint16_t filter_mask_high; /*!< filter mask number high bits */
uint16_t filter_mask_low; /*!< filter mask number low bits */
uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */
uint16_t filter_number; /*!< filter number */
uint16_t filter_mode; /*!< filter mode, list or mask */
uint16_t filter_bits; /*!< filter scale */
ControlStatus filter_enable; /*!< filter work or not */
}can_filter_parameter_struct;
/* CAN errors */
typedef enum
{
CAN_ERROR_NONE = 0, /*!< no error */
CAN_ERROR_FILL, /*!< fill error */
CAN_ERROR_FORMATE, /*!< format error */
CAN_ERROR_ACK, /*!< ACK error */
CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */
CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */
CAN_ERROR_CRC, /*!< CRC error */
CAN_ERROR_SOFTWARECFG, /*!< software configure */
}can_error_enum;
/* transmit states */
typedef enum
{
CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */
CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */
CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */
CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */
}can_transmit_state_enum;
/* CAN baudrate prescaler*/
#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0))
/* CAN bit segment 1*/
#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
/* CAN bit segment 2*/
#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
/* CAN resynchronization jump width*/
#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24))
/* CAN communication mode*/
#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30))
/* CAN FDATA high 16 bits */
#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))
/* CAN FDATA low 16 bits */
#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
/* CAN1 filter start bank_number*/
#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
/* CAN transmit mailbox extended identifier*/
#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3))
/* CAN transmit mailbox standard identifier*/
#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21))
/* transmit data byte 0 */
#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
/* transmit data byte 1 */
#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
/* transmit data byte 2 */
#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
/* transmit data byte 3 */
#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
/* transmit data byte 4 */
#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
/* transmit data byte 5 */
#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
/* transmit data byte 6 */
#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
/* transmit data byte 7 */
#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
/* receive mailbox extended identifier*/
#define RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31)
/* receive mailbox standrad identifier*/
#define RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31)
/* receive data length */
#define RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3)
/* the index of the filter by which the frame is passed */
#define RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15)
/* receive data byte 0 */
#define RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7)
/* receive data byte 1 */
#define RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15)
/* receive data byte 2 */
#define RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23)
/* receive data byte 3 */
#define RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31)
/* receive data byte 4 */
#define RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7)
/* receive data byte 5 */
#define RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15)
/* receive data byte 6 */
#define RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23)
/* receive data byte 7 */
#define RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31)
/* CAN errors */
#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
#define CAN_ERRN_0 ERR_ERRN(0) /* no error */
#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */
#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */
#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */
#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */
#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */
#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */
#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */
/* CAN phy mode bits */
#define PHYCTL_POMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
#define CAN_PHYCTL_POMODE_0 PHYCTL_POMOD(0) /*!< low slope mode */
#define CAN_PHYCTL_POMODE_1 PHYCTL_POMOD(1) /*!< middle slope mode */
#define CAN_PHYCTL_POMODE_2 PHYCTL_POMOD(2) /*!< high slope mode */
#define CAN_PHYCTL_POMODE_3 PHYCTL_POMOD(3) /*!< high speed mode */
#define CAN_PHYCTL_POMODE_MASK PHYCTL_POMOD(3) /*!< mask of phy mode */
#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */
/* CAN communication mode */
#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */
#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */
#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */
#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */
/* CAN resynchronisation jump width */
#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
/* CAN time segment 1 */
#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */
#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */
#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */
#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */
#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */
#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */
#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */
#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */
/* CAN time segment 2 */
#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
/* CAN mailbox number */
#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */
#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */
#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */
#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */
/* CAN frame format */
#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */
#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */
/* CAN receive fifo */
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */
/* frame number of receive fifo */
#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */
#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */
#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */
/* CAN working mode */
#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */
#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */
#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */
/* filter bits */
#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */
#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */
/* filter mode */
#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */
#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */
/* filter 16 bits mask */
#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU)
/* frame type */
#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */
#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */
/* CAN timeout */
#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */
/* interrupt enable bits */
#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */
#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */
#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */
#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */
#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */
#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */
#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */
#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */
#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */
#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */
#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */
#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */
#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */
#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */
/* function declarations */
/* deinitialize CAN */
void can_deinit(uint32_t can_periph);
/* initialize CAN */
ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init);
/* CAN filter init */
void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init);
/* set can1 fliter start bank number */
void can1_filter_start_bank(uint8_t start_bank);
/* enable functions */
/* CAN debug freeze enable */
void can_debug_freeze_enable(uint32_t can_periph);
/* CAN debug freeze disable */
void can_debug_freeze_disable(uint32_t can_periph);
/* CAN time triggle mode enable */
void can_time_trigger_mode_enable(uint32_t can_periph);
/* CAN time triggle mode disable */
void can_time_trigger_mode_disable(uint32_t can_periph);
/* transmit functions */
/* transmit CAN message */
uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message);
/* get CAN transmit state */
can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number);
/* stop CAN transmission */
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
/* CAN receive message */
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message);
/* CAN release fifo */
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
/* CAN receive message length */
uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number);
/* CAN working mode */
ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode);
/* CAN wakeup from sleep mode */
ErrStatus can_wakeup(uint32_t can_periph);
/* CAN get error */
can_error_enum can_error_get(uint32_t can_periph);
/* get CAN receive error number */
uint8_t can_receive_error_number_get(uint32_t can_periph);
/* get CAN transmit error number */
uint8_t can_transmit_error_number_get(uint32_t can_periph);
/* CAN interrupt enable */
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt);
/* CAN interrupt disable */
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt);
/* CAN get flag state */
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
/* CAN clear flag state */
void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
/* CAN get interrupt flag state */
FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag);
/* CAN clear interrupt flag state */
void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag);
/* enable CAN phy */
void can_phy_enable(uint32_t can_periph);
/* disable CAN phy */
void can_phy_disable(uint32_t can_periph);
/* set CAN PHY mode */
void can_phy_mode(uint32_t can_periph, uint32_t phy_mode);
#endif /* GD32F1X0_CAN_H */
#endif /* GD32F170_190 */

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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_cec.h Normal file
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/*!
\file gd32f1x0_cec.h
\brief definitions for the CEC
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_CEC_H
#define GD32F1X0_CEC_H
#include "gd32f1x0.h"
/* CEC definitions */
#define CEC CEC_BASE /*!< CEC base address */
/* registers definitions */
#define CEC_CTL REG32(CEC + 0x00U) /*!< CEC control register */
#define CEC_CFG REG32(CEC + 0x04U) /*!< CEC configuration register */
#define CEC_TDATA REG32(CEC + 0x08U) /*!< CEC transmit data register */
#define CEC_RDATA REG32(CEC + 0x0CU) /*!< CEC receive data register */
#define CEC_INTF REG32(CEC + 0x10U) /*!< CEC interrupt flag Register */
#define CEC_INTEN REG32(CEC + 0x14U) /*!< CEC interrupt enable register */
/* bits definitions */
/* CEC_CTL */
#define CEC_CTL_CECEN BIT(0) /*!< enable or disable HDMI-CEC controller bit */
#define CEC_CTL_STAOM BIT(1) /*!< start of sending a message. */
#define CEC_CTL_ENDOM BIT(2) /*!< ENDOM bit value in the next frame in Tx mode */
/* CEC_CFG */
#define CEC_CFG_SFT BITS(0,2) /*!< signal free time */
#define CEC_CFG_RTOL BIT(3) /*!< reception bit timing tolerance */
#define CEC_CFG_BRES BIT(4) /*!< whether stop receive message when detected BRE */
#define CEC_CFG_BREG BIT(5) /*!< generate Error-bit when detected BRE in singlecast */
#define CEC_CFG_BPLEG BIT(6) /*!< generate Error-bit when detected BPLE in singlecast */
#define CEC_CFG_BCNG BIT(7) /*!< do not generate Error-bit in broadcast message */
#define CEC_CFG_SFTOPT BIT(8) /*!< the SFT start option bit */
#define CEC_CFG_OAD BITS(16,30) /*!< own address */
#define CEC_CFG_LMEN BIT(31) /*!< listen mode enable bit */
/* CEC_TDATA */
#define CEC_TDATA_TDATA BITS(0,7) /*!< Tx data register */
/* CEC_RDATA */
#define CEC_RDATA_RDATA BITS(0,7) /*!< Rx data register */
/* CEC_INTF */
#define CEC_INTF_BR BIT(0) /*!< Rx-byte data received */
#define CEC_INTF_REND BIT(1) /*!< end of reception */
#define CEC_INTF_RO BIT(2) /*!< Rx overrun */
#define CEC_INTF_BRE BIT(3) /*!< bit rising error */
#define CEC_INTF_BPSE BIT(4) /*!< short bit period error */
#define CEC_INTF_BPLE BIT(5) /*!< long bit period error */
#define CEC_INTF_RAE BIT(6) /*!< Rx ACK error */
#define CEC_INTF_ARBF BIT(7) /*!< arbitration fail */
#define CEC_INTF_TBR BIT(8) /*!< Tx-byte data request */
#define CEC_INTF_TEND BIT(9) /*!< transmission successfully end */
#define CEC_INTF_TU BIT(10) /*!< Tx data buffer underrun */
#define CEC_INTF_TERR BIT(11) /*!< Tx-error */
#define CEC_INTF_TAERR BIT(12) /*!< Tx ACK error flag */
/* CEC_INTEN */
#define CEC_INTEN_BRIE BIT(0) /*!< BR interrupt enable */
#define CEC_INTEN_RENDIE BIT(1) /*!< REND interrupt enable */
#define CEC_INTEN_ROIE BIT(2) /*!< RO interrupt enable */
#define CEC_INTEN_BREIE BIT(3) /*!< BRE interrupt enable. */
#define CEC_INTEN_BPSEIE BIT(4) /*!< BPSE interrupt enable */
#define CEC_INTEN_BPLEIE BIT(5) /*!< BPLE interrupt enable. */
#define CEC_INTEN_RAEIE BIT(6) /*!< RAE interrupt enable */
#define CEC_INTEN_ARBFIE BIT(7) /*!< ARBF interrupt enable */
#define CEC_INTEN_TBRIE BIT(8) /*!< TBR interrupt enable */
#define CEC_INTEN_TENDIE BIT(9) /*!< TEND interrupt enable */
#define CEC_INTEN_TUIE BIT(10) /*!< TU interrupt enable */
#define CEC_INTEN_TERRIE BIT(11) /*!< TE interrupt enable */
#define CEC_INTEN_TAERRIE BIT(12) /*!< TAE interrupt enable */
/* constants definitions */
/* signal free time */
#define CFG_SFT(regval) (BITS(0, 2) & ((regval) << 0U))
#define CEC_SFT_PROTOCOL_PERIOD CFG_SFT(0) /*!< the signal free time will perform as HDMI-CEC protocol description */
#define CEC_SFT_1POINT5_PERIOD CFG_SFT(1) /*!< 1.5 nominal data bit periods */
#define CEC_SFT_2POINT5_PERIOD CFG_SFT(2) /*!< 2.5 nominal data bit periods */
#define CEC_SFT_3POINT5_PERIOD CFG_SFT(3) /*!< 3.5 nominal data bit periods */
#define CEC_SFT_4POINT5_PERIOD CFG_SFT(4) /*!< 4.5 nominal data bit periods */
#define CEC_SFT_5POINT5_PERIOD CFG_SFT(5) /*!< 5.5 nominal data bit periods */
#define CEC_SFT_6POINT5_PERIOD CFG_SFT(6) /*!< 6.5 nominal data bit periods */
#define CEC_SFT_7POINT5_PERIOD CFG_SFT(7) /*!< 7.5 nominal data bit periods */
/* signal free time start option */
#define CEC_SFT_START_STAOM ((uint32_t)0x00000000U) /*!< signal free time counter starts counting when STAOM is asserted */
#define CEC_SFT_START_LAST CEC_CFG_SFTOPT /*!< signal free time counter starts automatically after transmission/reception end */
/* own address */
#define CEC_OWN_ADDRESS_CLEAR ((uint32_t)0x00000000U) /*!< own address is cleared */
#define CEC_OWN_ADDRESS0 BIT(16) /*!< own address is 0 */
#define CEC_OWN_ADDRESS1 BIT(17) /*!< own address is 1 */
#define CEC_OWN_ADDRESS2 BIT(18) /*!< own address is 2 */
#define CEC_OWN_ADDRESS3 BIT(19) /*!< own address is 3 */
#define CEC_OWN_ADDRESS4 BIT(20) /*!< own address is 4 */
#define CEC_OWN_ADDRESS5 BIT(21) /*!< own address is 5 */
#define CEC_OWN_ADDRESS6 BIT(22) /*!< own address is 6 */
#define CEC_OWN_ADDRESS7 BIT(23) /*!< own address is 7 */
#define CEC_OWN_ADDRESS8 BIT(24) /*!< own address is 8 */
#define CEC_OWN_ADDRESS9 BIT(25) /*!< own address is 9 */
#define CEC_OWN_ADDRESS10 BIT(26) /*!< own address is 10 */
#define CEC_OWN_ADDRESS11 BIT(27) /*!< own address is 11 */
#define CEC_OWN_ADDRESS12 BIT(28) /*!< own address is 12 */
#define CEC_OWN_ADDRESS13 BIT(29) /*!< own address is 13 */
#define CEC_OWN_ADDRESS14 BIT(30) /*!< own address is 14 */
/* error-bit generate */
#define CEC_BROADCAST_ERROR_BIT_ON ((uint32_t)0x00000000U) /*!< generate Error-bit in broadcast */
#define CEC_BROADCAST_ERROR_BIT_OFF CEC_CFG_BCNG /*!< do not generate Error-bit in broadcast */
#define CEC_LONG_PERIOD_ERROR_BIT_OFF ((uint32_t)0x00000000U) /*!< generate Error-bit on long bit period error */
#define CEC_LONG_PERIOD_ERROR_BIT_ON CEC_CFG_BPLEG /*!< do not generate Error-bit on long bit period error */
#define CEC_RISING_PERIOD_ERROR_BIT_OFF ((uint32_t)0x00000000U) /*!< generate Error-bit on bit rising error */
#define CEC_RISING_PERIOD_ERROR_BIT_ON CEC_CFG_BREG /*!< do not generate Error-bit on bit rising error */
/* whether stop receive message when detected bit rising error */
#define CEC_STOP_RISING_ERROR_BIT_ON ((uint32_t)0x00000000U) /*!< stop reception when detected bit rising error */
#define CEC_STOP_RISING_ERROR_BIT_OFF ((uint32_t)0x00000001U) /*!< do not stop reception when detected bit rising error */
/* flag bits */
#define CEC_FLAG_BR CEC_INTF_BR /*!< RX-byte data received */
#define CEC_FLAG_REND CEC_INTF_REND /*!< end of reception */
#define CEC_FLAG_RO CEC_INTF_RO /*!< RX overrun */
#define CEC_FLAG_BRE CEC_INTF_BRE /*!< bit rising error */
#define CEC_FLAG_BPSE CEC_INTF_BPSE /*!< short bit period error */
#define CEC_FLAG_BPLE CEC_INTF_BPLE /*!< long bit period error */
#define CEC_FLAG_RAE CEC_INTF_RAE /*!< RX ACK error */
#define CEC_FLAG_ARBF CEC_INTF_ARBF /*!< arbitration lost */
#define CEC_FLAG_TBR CEC_INTF_TBR /*!< TX-byte data request */
#define CEC_FLAG_TEND CEC_INTF_TEND /*!< transmission successfully end */
#define CEC_FLAG_TU CEC_INTF_TU /*!< TX data buffer underrun */
#define CEC_FLAG_TERR CEC_INTF_TERR /*!< TX-error */
#define CEC_FLAG_TAERR CEC_INTF_TAERR /*!< TX ACK error flag */
/* interrupt flag bits */
#define CEC_INT_FLAG_BR CEC_INTF_BR /*!< RX-byte data received */
#define CEC_INT_FLAG_REND CEC_INTF_REND /*!< end of reception */
#define CEC_INT_FLAG_RO CEC_INTF_RO /*!< RX overrun */
#define CEC_INT_FLAG_BRE CEC_INTF_BRE /*!< bit rising error */
#define CEC_INT_FLAG_BPSE CEC_INTF_BPSE /*!< short bit period error */
#define CEC_INT_FLAG_BPLE CEC_INTF_BPLE /*!< long bit period error */
#define CEC_INT_FLAG_RAE CEC_INTF_RAE /*!< RX ACK error */
#define CEC_INT_FLAG_ARBF CEC_INTF_ARBF /*!< arbitration lost */
#define CEC_INT_FLAG_TBR CEC_INTF_TBR /*!< TX-byte data request */
#define CEC_INT_FLAG_TEND CEC_INTF_TEND /*!< transmission successfully end */
#define CEC_INT_FLAG_TU CEC_INTF_TU /*!< TX data buffer underrun */
#define CEC_INT_FLAG_TERR CEC_INTF_TERR /*!< TX-error */
#define CEC_INT_FLAG_TAERR CEC_INTF_TAERR /*!< TX ACK error flag */
/* interrupt enable bits */
#define CEC_INT_BR CEC_INTEN_BRIE /*!< BR interrupt enable */
#define CEC_INT_REND CEC_INTEN_RENDIE /*!< REND interrupt enable */
#define CEC_INT_RO CEC_INTEN_ROIE /*!< RO interrupt enable */
#define CEC_INT_BRE CEC_INTEN_BREIE /*!< BRE interrupt enable. */
#define CEC_INT_BPSE CEC_INTEN_BPSEIE /*!< BPSE interrupt enable */
#define CEC_INT_BPLE CEC_INTEN_BPLEIE /*!< BPLE interrupt enable. */
#define CEC_INT_RAE CEC_INTEN_RAEIE /*!< RAE interrupt enable */
#define CEC_INT_ARBF CEC_INTEN_ARBFIE /*!< ALRLST interrupt enable */
#define CEC_INT_TBR CEC_INTEN_TBRIE /*!< TBR interrupt enable */
#define CEC_INT_TEND CEC_INTEN_TENDIE /*!< TEND interrupt enable */
#define CEC_INT_TU CEC_INTEN_TUIE /*!< TU interrupt enable */
#define CEC_INT_TERR CEC_INTEN_TERRIE /*!< TE interrupt enable */
#define CEC_INT_TAERR CEC_INTEN_TAERRIE /*!< TAE interrupt enable */
/* function declarations */
/* reset HDMI-CEC controller */
void cec_deinit(void);
/* configure signal free time,the signal free time counter start option,own address */
void cec_init(uint32_t sftmopt, uint32_t sft, uint32_t address);
/* configure generate Error-bit, whether stop receive message when detected bit rising error */
void cec_error_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre, uint32_t rxbrestp);
/* enable HDMI-CEC controller */
void cec_enable(void);
/* disable HDMI-CEC controller */
void cec_disable(void);
/* start CEC message transmission */
void cec_transmission_start(void);
/* end CEC message transmission */
void cec_transmission_end(void);
/* enable CEC listen mode */
void cec_listen_mode_enable(void);
/* disable CEC listen mode */
void cec_listen_mode_disable(void);
/* configure and clear own address */
void cec_own_address_config(uint32_t address);
/* configure signal free time and the signal free time counter start option */
void cec_sft_config(uint32_t sftmopt,uint32_t sft);
/* configure generate Error-bit when detected some abnormal situation or not */
void cec_generate_errorbit_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre);
/* whether stop receive message when detected bit rising error */
void cec_stop_receive_bre_config(uint32_t rxbrestp);
/* enable reception bit timing tolerance */
void cec_reception_tolerance_enable(void);
/* disable reception bit timing tolerance */
void cec_reception_tolerance_disable(void);
/* send a data by the CEC peripheral */
void cec_data_send(uint8_t data);
/* receive a data by the CEC peripheral */
uint8_t cec_data_receive(void);
/* clear CEC int flag and status */
FlagStatus cec_interrupt_flag_get(uint32_t flag);
/* clear CEC flag */
void cec_interrupt_flag_clear(uint32_t flag);
/* enable interrupt */
void cec_interrupt_enable(uint32_t flag);
/* disable interrupt */
void cec_interrupt_disable(uint32_t flag);
/* get CEC status */
FlagStatus cec_flag_get(uint32_t flag);
/* clear CEC status */
void cec_flag_clear(uint32_t flag);
#endif /* GD32F1X0_CEC_H */

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/*!
\file gd32f1x0_cmp.h
\brief definitions for the CMP
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=5)
2016-01-15, V2.0.0, platform GD32F1x0(x=5,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=5,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=5,9)
*/
#ifndef GD32F1X0_CMP_H
#define GD32F1X0_CMP_H
#include "gd32f1x0.h"
/* CMP definitions */
#define CMP CMP_BASE /*!< CMP base address */
/* registers definitions */
#define CMP_CS REG32((CMP) + 0x00U) /*!< CMP control and status register */
/* CMP_CS bits definitions */
#define CMP_CS_CMP0EN BIT(0) /*!< CMP0 enable */
#define CMP_CS_CMP0SW BIT(1) /*!< CMP0 switch */
#define CMP_CS_CMP0M BITS(2,3) /*!< CMP0 mode */
#define CMP_CS_CMP0MSEL BITS(4,6) /*!< COMP0_M input selection */
#define CMP_CS_CMP0OSEL BITS(8,10) /*!< CMP0 output selection */
#define CMP_CS_CMP0PL BIT(11) /*!< polarity of CMP0 output */
#define CMP_CS_CMP0HST BITS(12,13) /*!< CMP0 hysteresis */
#define CMP_CS_CMP0O BIT(14) /*!< CMP0 output */
#define CMP_CS_CMP0LK BIT(15) /*!< CMP0 lock */
#define CMP_CS_CMP1EN BIT(16) /*!< CMP1 enable */
#define CMP_CS_CMP1M BITS(18,19) /*!< CMP1 mode */
#define CMP_CS_CMP1MSEL BITS(20,22) /*!< CMP1_M input selection */
#define CMP_CS_WNDEN BIT(23) /*!< window mode enable */
#define CMP_CS_CMP1OSEL BITS(24,26) /*!< CMP1 output selection */
#define CMP_CS_CMP1PL BIT(27) /*!< polarity of CMP1 output */
#define CMP_CS_CMP1HST BITS(28,29) /*!< CMP1 hysteresis */
#define CMP_CS_CMP1O BIT(30) /*!< CMP1 output */
#define CMP_CS_CMP1LK BIT(31) /*!< CMP1 lock */
/* consts definitions */
/* operating mode */
typedef enum{
CMP_HIGHSPEED = 0, /*!< high speed mode */
CMP_MIDDLESPEED, /*!< medium speed mode */
CMP_LOWSPEED, /*!< low speed mode */
CMP_VERYLOWSPEED /*!< very-low speed mode */
}operating_mode_enum;
/* inverting input */
typedef enum{
CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */
CMP_1_2VREFINT, /*!< VREFINT /2 input */
CMP_3_4VREFINT, /*!< VREFINT *3/4 input */
CMP_VREFINT, /*!< VREFINT input */
CMP_DAC0, /*!< PA4 (DAC0) input */
#ifdef GD32F170_190
CMP_DAC1, /*!< DAC1 input */
#else
CMP_PA5, /*!< PA5 input */
#endif
CMP_PA_0_2 /*!< PA0 input when CMP0 is selected, PA2 input when CMP1 is selected */
}inverting_input_enum;
/* hysteresis */
typedef enum{
CMP_HYSTERESIS_NO = 0, /*!< output no hysteresis */
CMP_HYSTERESIS_LOW, /*!< output low hysteresis */
CMP_HYSTERESIS_MIDDLE, /*!< output middle hysteresis */
CMP_HYSTERESIS_HIGH /*!< output high hysteresis */
}cmp_hysteresis_enum;
/* output */
typedef enum{
CMP_OUTPUT_NONE = 0, /*!< output no selection */
CMP_OUTPUT_TIMER0BKIN, /*!< TIMER 0 break input */
CMP_OUTPUT_TIMER0IC0, /*!< TIMER 0 channel0 input capture */
CMP_OUTPUT_TIMER0OCPRECLR, /*!< TIMER 0 OCPRE_CLR input */
CMP_OUTPUT_TIMER1IC3, /*!< TIMER 1 channel3 input capture */
CMP_OUTPUT_TIMER1OCPRECLR, /*!< TIMER 1 OCPRE_CLR input */
CMP_OUTPUT_TIMER2IC0, /*!< TIMER 2 channel0 input capture */
CMP_OUTPUT_TIMER2OCPRECLR /*!< TIMER 2 OCPRE_CLR input */
}cmp_output_enum;
/* CMP0 mode */
#define CS_CMP0M(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
#define CS_CMP0M_HIGHSPEED CS_CMP0M(0) /*!< CMP0 mode high speed */
#define CS_CMP0M_MIDDLESPEED CS_CMP0M(1) /*!< CMP0 mode middle speed */
#define CS_CMP0M_LOWSPEED CS_CMP0M(2) /*!< CMP0 mode low speed */
#define CS_CMP0M_VERYLOWSPEED CS_CMP0M(3) /*!< CMP0 mode very low speed */
/* comparator 0 inverting input */
#define CS_CMP0MSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
#define CS_CMP0MSEL_1_4VREFINT CS_CMP0MSEL(0) /*!< CMP0 inverting input 1/4 Vrefint */
#define CS_CMP0MSEL_1_2VREFINT CS_CMP0MSEL(1) /*!< CMP0 inverting input 1/2 Vrefint */
#define CS_CMP0MSEL_3_4VREFINT CS_CMP0MSEL(2) /*!< CMP0 inverting input 3/4 Vrefint */
#define CS_CMP0MSEL_VREFINT CS_CMP0MSEL(3) /*!< CMP0 inverting input Vrefint */
#define CS_CMP0MSEL_DAC0 CS_CMP0MSEL(4) /*!< CMP0 inverting input DAC0*/
#define CS_CMP0MSEL_PA5 CS_CMP0MSEL(5) /*!< CMP0 inverting input PA5*/
#define CS_CMP0MSEL_PA0 CS_CMP0MSEL(6) /*!< CMP0 inverting input PA0*/
/* CMP0 output */
#define CS_CMP0OSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
#define CS_CMP0OSEL_OUTPUT_NONE CS_CMP0OSEL(0) /*!< CMP0 output none */
#define CS_CMP0OSEL_OUTPUT_TIMER0BKIN CS_CMP0OSEL(1) /*!< CMP0 output TIMER 0 break input */
#define CS_CMP0OSEL_OUTPUT_TIMER0IC0 CS_CMP0OSEL(2) /*!< CMP0 output TIMER 0 channel 0 input capture */
#define CS_CMP0OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP0OSEL(3) /*!< CMP0 output TIMER 0 ocpreclear input */
#define CS_CMP0OSEL_OUTPUT_TIMER1IC3 CS_CMP0OSEL(4) /*!< CMP0 output TIMER 1 channel 3 input capture */
#define CS_CMP0OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP0OSEL(5) /*!< CMP0 output TIMER 1 ocpreclear input */
#define CS_CMP0OSEL_OUTPUT_TIMER2IC0 CS_CMP0OSEL(6) /*!< CMP0 output TIMER 2 channle 0 input capture */
#define CS_CMP0OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP0OSEL(7) /*!< CMP0 output TIMER 2 ocpreclear input */
/* CMP0 hysteresis */
#define CS_CMP0HST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
#define CS_CMP0HST_HYSTERESIS_NO CS_CMP0HST(0) /*!< CMP0 output no hysteresis */
#define CS_CMP0HST_HYSTERESIS_LOW CS_CMP0HST(1) /*!< CMP0 output low hysteresis */
#define CS_CMP0HST_HYSTERESIS_MIDDLE CS_CMP0HST(2) /*!< CMP0 output middle hysteresis */
#define CS_CMP0HST_HYSTERESIS_HIGH CS_CMP0HST(3) /*!< CMP0 output high hysteresis */
/* CMP1 mode */
#define CS_CMP1M(regval) (BITS(18,19) & ((uint32_t)(regval) << 18))
#define CS_CMP1M_HIGHSPEED CS_CMP1M(0) /*!< CMP1 mode high speed */
#define CS_CMP1M_MIDDLESPEED CS_CMP1M(1) /*!< CMP1 mode middle speed */
#define CS_CMP1M_LOWSPEED CS_CMP1M(2) /*!< CMP1 mode low speed */
#define CS_CMP1M_VERYLOWSPEED CS_CMP1M(3) /*!< CMP1 mode very low speed */
/* CMP1 inverting input */
#define CS_CMP1MSEL(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
#define CS_CMP1MSEL_1_4VREFINT CS_CMP1MSEL(0) /*!< CMP1 inverting input 1/4 Vrefint */
#define CS_CMP1MSEL_1_2VREFINT CS_CMP1MSEL(1) /*!< CMP1 inverting input 1/2 Vrefint */
#define CS_CMP1MSEL_3_4VREFINT CS_CMP1MSEL(2) /*!< CMP1 inverting input 3/4 Vrefint */
#define CS_CMP1MSEL_VREFINT CS_CMP1MSEL(3) /*!< CMP1 inverting input Vrefint */
#define CS_CMP1MSEL_DAC0 CS_CMP1MSEL(4) /*!< CMP1 inverting input DAC0*/
#ifdef GD32F170_190
#define CS_CMP1MSEL_PA5 CS_CMP1MSEL(5) /*!< CMP1 inverting input PA5*/
#else
#define CS_CMP1MSEL_DAC1 CS_CMP1MSEL(5) /*!< CMP1 inverting input DAC1*/
#endif
#define CS_CMP1MSEL_PA2 CS_CMP1MSEL(6) /*!< CMP1 inverting input PA2*/
/* comparator channel1 output */
#define CS_CMP1OSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
#define CS_CMP1OSEL_OUTPUT_NONE CS_CMP1OSEL(0) /*!< CMP1 output none */
#define CS_CMP1OSEL_OUTPUT_TIMER0BKIN CS_CMP1OSEL(1) /*!< CMP1 output TIMER 0 break input */
#define CS_CMP1OSEL_OUTPUT_TIMER0IC0 CS_CMP1OSEL(2) /*!< CMP1 output TIMER 0 channel 0 input capture */
#define CS_CMP1OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP1OSEL(3) /*!< CMP1 output TIMER 0 ocpreclear input */
#define CS_CMP1OSEL_OUTPUT_TIMER1IC3 CS_CMP1OSEL(4) /*!< CMP1 output TIMER 1 channel 3 input capture */
#define CS_CMP1OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP1OSEL(5) /*!< CMP1 output TIMER 1 ocpreclear input */
#define CS_CMP1OSEL_OUTPUT_TIMER2IC0 CS_CMP1OSEL(6) /*!< CMP1 output TIMER 2 channle 0 input capture */
#define CS_CMP1OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP1OSEL(7) /*!< CMP1 output TIMER 2 ocpreclear input */
/* CMP1 hysteresis */
#define CS_CMP1HST(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
#define CS_CMP1HST_HSTHYSTERESIS_NO CS_CMP1HST(0) /*!< CMP1 output no hysteresis */
#define CS_CMP1HST_HYSTERESIS_LOW CS_CMP1HST(1) /*!< CMP1 output low hysteresis */
#define CS_CMP1HST_HYSTERESIS_MIDDLE CS_CMP1HST(2) /*!< CMP1 output middle hysteresis */
#define CS_CMP1HST_HYSTERESIS_HIGH CS_CMP1HST(3) /*!< CMP1 output high hysteresis */
/* comparator x definitions */
#define CMP0 ((uint32_t)0x00000000) /*!< comparator 0 */
#define CMP1 ((uint32_t)0x00000010) /*!< comparator 1 */
/* comparator output level */
#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001) /*!< comparator output high */
#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) /*!< comparator output low */
/* output polarity of comparator */
#define CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001) /*!< output is inverted */
#define CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000) /*!< output is not inverted */
/* function declarations */
/* initialization functions */
/* CMP deinit */
void cmp_deinit(void);
/* CMP mode init */
void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum cmp_operating_mode, inverting_input_enum cmp_inverting_input, cmp_hysteresis_enum output_hysteresis);
/* CMP output init */
void cmp_output_init(uint32_t cmp_periph, cmp_output_enum cmp_output_slection, uint32_t cmp_output_polarity);
/* enable functions */
/* enable CMP */
void cmp_enable(uint32_t cmp_periph);
/* disable CMP */
void cmp_disable(uint32_t cmp_periph);
/* enable CMP switch */
void cmp_switch_enable(void);
/* disable CMP switch */
void cmp_switch_disable(void);
/* enable the window mode */
void cmp_window_enable(void);
/* disable the window mode */
void cmp_window_disable(void);
/* lock the CMP */
void cmp_lock_enable(uint32_t cmp_periph);
/* unlock the CMP */
void cmp_lock_disable(uint32_t cmp_periph);
/* output functions */
/* get output level */
uint32_t cmp_output_level_get(uint32_t cmp_periph);
#endif /* GD32F1X0_CMP_H */

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/*!
\file gd32f1x0_crc.h
\brief definitions for the CRC
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_CRC_H
#define GD32F1X0_CRC_H
#include "gd32f1x0.h"
/* CRC definitions */
#define CRC CRC_BASE
/* registers definitions */
#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */
#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */
#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
#define CRC_IDATA REG32(CRC + 0x10U) /*!< CRC initialization data register */
/* bits definitions */
/* CRC_DATA */
#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */
/* CRC_FDATA */
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
/* CRC_CTL */
#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */
#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */
#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */
/* CRC_IDATA */
#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */
/* constants definitions */
/* input data reverse function */
#define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5))
#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */
#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */
#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */
#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */
/* function declarations */
/* deinit CRC calculation unit */
void crc_deinit(void);
/* enable the reverse operation of output data */
void crc_reverse_output_data_enable(void);
/* disable the reverse operation of output data */
void crc_reverse_output_data_disable(void);
/* reset data register to the value of initializaiton data register */
void crc_data_register_reset(void);
/* read the data register */
uint32_t crc_data_register_read(void);
/* read the free data register */
uint8_t crc_free_data_register_read(void);
/* write the free data register */
void crc_free_data_register_write(uint8_t free_data);
/* write the initializaiton data register */
void crc_init_data_register_write(uint32_t init_data);
/* configure the CRC input data function */
void crc_input_data_reverse_config(uint32_t data_reverse);
/* CRC calculate a 32-bit data */
uint32_t crc_single_data_calculate(uint32_t sdata);
/* CRC calculate a 32-bit data array */
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
#endif /* GD32F1X0_CRC_H */

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/*!
\file gd32f1x0_dac.h
\brief definitions for the DAC
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_DAC_H
#define GD32F1X0_DAC_H
#include "gd32f1x0.h"
/* DACx(x=0,1) definitions */
#define DAC DAC_BASE
#define DAC0 0U
#ifdef GD32F170_190
#define DAC1 1U
#endif /* GD32F170_190 */
/* registers definitions */
#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */
#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */
#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */
#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */
#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */
#ifdef GD32F170_190
#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */
#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */
#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */
#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */
#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */
#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */
#endif /* GD32F170_190 */
#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 output data register */
#ifdef GD32F170_190
#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 output data register */
#endif /* GD32F170_190 */
#define DAC_STAT REG32(DAC + 0x34U) /*!< DAC status register */
/* bits definitions */
/* DAC_CTL */
#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */
#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */
#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */
#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */
#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disanle bit */
#define DAC_CTL_DDUDRIE0 BIT(13) /*!< DAC0 DMA underrun Interrupt enable/disable bit */
#ifdef GD32F170_190
#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */
#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */
#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */
#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */
#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */
#define DAC_CTL_DDUDRIE1 BIT(29) /*!< DAC1 DMA underrun interrupt enable/disable bit */
#endif /* GD32F170_190 */
/* DAC_SWT */
#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit,cleared by hardware */
#ifdef GD32F170_190
#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit,cleared by hardware */
#endif /* GD32F170_190 */
/* DAC0_R12DH */
#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */
/* DAC0_L12DH */
#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */
/* DAC0_R8DH */
#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */
#ifdef GD32F170_190
/* DAC1_R12DH */
#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */
/* DAC1_L12DH */
#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */
/* DAC1_R8DH */
#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */
/* DACC_R12DH */
#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */
#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */
/* DACC_L12DH */
#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */
#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */
/* DACC_R8DH */
#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */
#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */
#endif /* GD32F170_190 */
/* DAC0_DO */
#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */
#ifdef GD32F170_190
/* DAC1_DO */
#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */
#endif /* GD32F170_190 */
/* DAC_STAT */
#define DAC_STAT_DDUDR0 BIT(13) /*!< DAC0 DMA underrun flag */
#ifdef GD32F170_190
#define DAC_STAT_DDUDR1 BIT(29) /*!< DAC1 DMA underrun flag */
#endif /* GD32F170_190 */
/* constants definitions */
/* DAC trigger source */
#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */
#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */
#define DAC_TRIGGER_T14_TRGO CTL_DTSEL(3) /*!< TIMER14 TRGO */
#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */
#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */
#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */
/* dac data alignment */
#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */
#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */
#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */
/* function declarations */
/* deinit DAC */
void dac_deinit(void);
/* enable DAC0 function */
void dac0_enable(void);
/* disable DAC0 function */
void dac0_disable(void);
/* enable DAC0 DMA function */
void dac0_dma_enable(void);
/* disable DAC0 DMA function */
void dac0_dma_disable(void);
/* enable DAC0 output buffer function */
void dac0_output_buffer_enable(void);
/* disable DAC0 output buffer function */
void dac0_output_buffer_disable(void);
/* enable DAC0 trigger function */
void dac0_trigger_enable(void);
/* disable DAC0 trigger function */
void dac0_trigger_disable(void);
/* enable DAC0 software trigger function */
void dac0_software_trigger_enable(void);
/* disable DAC0 software trigger function */
void dac0_software_trigger_disable(void);
/* enable DAC0 interrupt(DAC0 DMA underrun interrupt) */
void dac0_interrupt_enable(void);
/* disable DAC0 interrupt(DAC0 DMA underrun interrupt) */
void dac0_interrupt_disable(void);
/* set DAC0 tgigger source function */
void dac0_trigger_source_config(uint32_t triggersource);
/* get the last data output value */
uint16_t dac0_output_value_get(void);
/* get the specified DAC0 flag(DAC0 DMA underrun flag) */
FlagStatus dac0_flag_get(void);
/* clear the specified DAC0 flag(DAC0 DMA underrun flag) */
void dac0_flag_clear(void);
/* get the specified DAC0 interrupt flag(DAC0 DMA underrun interrupt flag) */
FlagStatus dac0_interrupt_flag_get(void);
/* clear the specified DAC0 interrupt flag(DAC0 DMA underrun interrupt flag) */
void dac0_interrupt_flag_clear(void);
/* set DAC0 data holding register value */
void dac0_data_set(uint32_t dac_align, uint16_t data);
#ifdef GD32F170_190
/* enable DAC */
void dac_enable(uint32_t dac_periph);
/* disable DAC */
void dac_disable(uint32_t dac_periph);
/* enable DAC DMA */
void dac_dma_enable(uint32_t dac_periph);
/* disable DAC DMA */
void dac_dma_disable(uint32_t dac_periph);
/* enable DAC output buffer */
void dac_output_buffer_enable(uint32_t dac_periph);
/* disable DAC output buffer */
void dac_output_buffer_disable(uint32_t dac_periph);
/* enable DAC trigger */
void dac_trigger_enable(uint32_t dac_periph);
/* disable DAC trigger */
void dac_trigger_disable(uint32_t dac_periph);
/* enable DAC software trigger */
void dac_software_trigger_enable(uint32_t dac_periph);
/* disable DAC software trigger */
void dac_software_trigger_disable(uint32_t dac_periph);
/* enable DAC interrupt(DAC0 DMA underrun interrupt) */
void dac_interrupt_enable(uint32_t dac_periph);
/* disable DAC interrupt(DAC0 DMA underrun interrupt) */
void dac_interrupt_disable(uint32_t dac_periph);
/* set DAC tgigger source */
void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource);
/* get the last data output value */
uint16_t dac_output_value_get(uint32_t dac_periph);
/* get the specified DAC flag(DAC DMA underrun flag) */
FlagStatus dac_flag_get(uint32_t dac_periph);
/* clear the specified DAC flag(DAC DMA underrun flag) */
void dac_flag_clear(uint32_t dac_periph);
/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
FlagStatus dac_interrupt_flag_get(uint32_t dac_periph);
/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
void dac_interrupt_flag_clear(uint32_t dac_periph);
/* enable DAC concurrent mode */
void dac_concurrent_enable(void);
/* disable DAC concurrent mode */
void dac_concurrent_disable(void);
/* enable DAC concurrent software trigger */
void dac_concurrent_software_trigger_enable(void);
/* disable DAC concurrent software trigger */
void dac_concurrent_software_trigger_disable(void);
/* enable DAC concurrent buffer */
void dac_concurrent_output_buffer_enable(void);
/* disable DAC concurrent buffer */
void dac_concurrent_output_buffer_disable(void);
/* enable DAC concurrent interrupt */
void dac_concurrent_interrupt_enable(void);
/* disable DAC concurrent interrupt */
void dac_concurrent_interrupt_disable(void);
/* set DAC data holding register value */
void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data);
/* set DAC concurrent mode data holding register value */
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data1, uint16_t data2);
#endif /* GD32F170_190 */
#endif /* GD32F1X0_DAC_H */

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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_dbg.h Normal file
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/*!
\file gd32f1x0_dbg.h
\brief definitions for the DBG
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_DBG_H
#define GD32F1X0_DBG_H
#include "gd32f1x0.h"
/* DBG definitions */
#define DBG DBG_BASE
/* registers definitions */
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */
#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */
/* bits definitions */
/* DBG_ID */
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
/* DBG_CTL0 */
#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< TIMER0 counter kept when core is halted */
#define DBG_CTL0_TIMER1_HOLD BIT(11) /*!< TIMER1 counter kept when core is halted */
#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< TIMER2 counter kept when core is halted */
#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
#define DBG_CTL0_I2C2_HOLD BIT(17) /*!< hold I2C2 smbus when core is halted */
#ifdef GD32F170_190
#define DBG_CTL0_CAN0_HOLD BIT(18) /*!< CAN0 counter kept when core is halted */
#endif /* GD32F170_190 */
#define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
#ifdef GD32F170_190
#define DBG_CTL0_CAN1_HOLD BIT(21) /*!< hold CAN1 counter when core is halted */
#endif /* GD32F170_190 */
#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */
/* DBG_CTL1 */
#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */
#define DBG_CTL1_TIMER14_HOLD BIT(16) /*!< hold TIMER14 counter when core is halted */
#define DBG_CTL1_TIMER15_HOLD BIT(17) /*!< hold TIMER15 counter when core is halted */
#define DBG_CTL1_TIMER16_HOLD BIT(18) /*!< hold TIMER16 counter when core is halted */
/* constants definitions */
#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
/* define the peripheral debug hold bit position and its register index offset */
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
/* register index */
enum dbg_reg_idx
{
DBG_IDX_CTL0 = 0x04U,
DBG_IDX_CTL1 = 0x08U,
};
/* peripherals hold bit */
typedef enum
{
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< FWDGT hold bit */
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< WWDGT hold bit */
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< TIMER0 hold bit */
DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 11U), /*!< TIMER1 hold bit */
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< TIMER2 hold bit */
#ifdef GD32F170_190
DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 14U), /*!< CAN0 hold bit */
#endif /* GD32F170_190 */
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< I2C0 hold bit */
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< I2C1 hold bit */
DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 17U), /*!< I2C2 hold bit */
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< TIMER5 hold bit */
#ifdef GD32F170_190
DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 21U), /*!< CAN1 hold bit */
#endif /* GD32F170_190 */
DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< TIMER13 hold bit */
DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< RTC hold bit */
DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< TIMER14 hold bit */
DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< TIMER15 hold bit */
DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), /*!< TIMER16 hold bit */
}dbg_periph_enum;
/* function declarations */
/* deinitialize the DBG */
void dbg_deinit(void);
/* read DBG_ID code register */
uint32_t dbg_id_get(void);
/* enable low power behavior when the MCU is in debug mode */
void dbg_low_power_enable(uint32_t dbg_low_power);
/* disable low power behavior when the MCU is in debug mode */
void dbg_low_power_disable(uint32_t dbg_low_power);
/* enable peripheral behavior when the MCU is in debug mode */
void dbg_periph_enable(dbg_periph_enum dbg_periph);
/* disable peripheral behavior when the MCU is in debug mode */
void dbg_periph_disable(dbg_periph_enum dbg_periph);
#endif /* GD32F1X0_DBG_H */

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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_dma.h Normal file
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/*!
\file gd32f1x0_dma.h
\brief definitions for the DMA
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_DMA_H
#define GD32F1X0_DMA_H
#include "gd32f1x0.h"
/* DMA definitions */
#define DMA DMA_BASE /*!< DMA base address */
/* registers definitions */
#define DMA_INTF REG32(DMA + 0x00U) /*!< DMA interrupt flag register */
#define DMA_INTC REG32(DMA + 0x04U) /*!< DMA interrupt flag clear register */
#define DMA_CH0CTL REG32(DMA + 0x08U) /*!< DMA channel 0 control register */
#define DMA_CH0CNT REG32(DMA + 0x0CU) /*!< DMA channel 0 counter register */
#define DMA_CH0PADDR REG32(DMA + 0x10U) /*!< DMA channel 0 peripheral base address register */
#define DMA_CH0MADDR REG32(DMA + 0x14U) /*!< DMA channel 0 memory base address register */
#define DMA_CH1CTL REG32(DMA + 0x1CU) /*!< DMA channel 1 control register */
#define DMA_CH1CNT REG32(DMA + 0x20U) /*!< DMA channel 1 counter register */
#define DMA_CH1PADDR REG32(DMA + 0x24U) /*!< DMA channel 1 peripheral base address register */
#define DMA_CH1MADDR REG32(DMA + 0x28U) /*!< DMA channel 1 memory base address register */
#define DMA_CH2CTL REG32(DMA + 0x30U) /*!< DMA channel 2 control register */
#define DMA_CH2CNT REG32(DMA + 0x34U) /*!< DMA channel 2 counter register */
#define DMA_CH2PADDR REG32(DMA + 0x38U) /*!< DMA channel 2 peripheral base address register */
#define DMA_CH2MADDR REG32(DMA + 0x3CU) /*!< DMA channel 2 memory base address register */
#define DMA_CH3CTL REG32(DMA + 0x44U) /*!< DMA channel 3 control register */
#define DMA_CH3CNT REG32(DMA + 0x48U) /*!< DMA channel 3 counter register */
#define DMA_CH3PADDR REG32(DMA + 0x4CU) /*!< DMA channel 3 peripheral base address register */
#define DMA_CH3MADDR REG32(DMA + 0x50U) /*!< DMA channel 3 memory base address register */
#define DMA_CH4CTL REG32(DMA + 0x58U) /*!< DMA channel 4 control register */
#define DMA_CH4CNT REG32(DMA + 0x5CU) /*!< DMA channel 4 counter register */
#define DMA_CH4PADDR REG32(DMA + 0x60U) /*!< DMA channel 4 peripheral base address register */
#define DMA_CH4MADDR REG32(DMA + 0x64U) /*!< DMA channel 4 memory base address register */
#define DMA_CH5CTL REG32(DMA + 0x6CU) /*!< DMA channel 5 control register */
#define DMA_CH5CNT REG32(DMA + 0x70U) /*!< DMA channel 5 counter register */
#define DMA_CH5PADDR REG32(DMA + 0x74U) /*!< DMA channel 5 peripheral base address register */
#define DMA_CH5MADDR REG32(DMA + 0x78U) /*!< DMA channel 5 memory base address register */
#define DMA_CH6CTL REG32(DMA + 0x80U) /*!< DMA channel 6 control register */
#define DMA_CH6CNT REG32(DMA + 0x84U) /*!< DMA channel 6 counter register */
#define DMA_CH6PADDR REG32(DMA + 0x88U) /*!< DMA channel 6 peripheral base address register */
#define DMA_CH6MADDR REG32(DMA + 0x8CU) /*!< DMA channel 6 memory base address register */
/* bits definitions */
/* DMA_INTF */
#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */
#define DMA_INTF_FTFIF BIT(1) /*!< transfer complete flag of channel */
#define DMA_INTF_HTFIF BIT(2) /*!< half transfer complete flag of channel */
#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
/* DMA_INTC */
#define DMA_INTFC_GIFC BIT(0) /*!< clear global interrupt flag of channel */
#define DMA_INTFC_FTFIFC BIT(1) /*!< clear transfer complete flag of channel */
#define DMA_INTFC_HTFIFC BIT(2) /*!< clear half transfer complete flag of channel */
#define DMA_INTFC_ERRIFC BIT(3) /*!< clear error flag of channel */
/* DMA_CHxCTL,x=0..6 */
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */
#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */
#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */
#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */
#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */
#define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */
#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */
#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */
#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */
#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
/* DMA_CHxCNT, x=0..6 */
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
/* DMA_CHxPADDR, x=0..6 */
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
/* DMA_CHxMADDR, x=0..6 */
#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */
/* constants definitions */
/* DMA channel select */
typedef enum
{
DMA_CH0 = 0, /*!< DMA Channel0 */
DMA_CH1, /*!< DMA Channel1 */
DMA_CH2, /*!< DMA Channel2 */
DMA_CH3, /*!< DMA Channel3 */
DMA_CH4, /*!< DMA Channel4 */
DMA_CH5, /*!< DMA Channel5 */
DMA_CH6 /*!< DMA Channel6 */
} dma_channel_enum;
/* DMA initialize struct */
typedef struct
{
uint32_t periph_addr; /*!< peripheral base address */
uint32_t periph_width; /*!< transfer data size of peripheral */
uint32_t periph_inc; /*!< peripheral increasing mode */
uint32_t memory_addr; /*!< memory base address */
uint32_t memory_width; /*!< transfer data size of memory */
uint32_t memory_inc; /*!< memory increasing mode */
uint32_t direction; /*!< channel data transfer direction */
uint32_t number; /*!< channel transfer number */
uint32_t priority; /*!< channel priority level */
} dma_parameter_struct;
/* flag bits */
#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */
#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */
/* interrupt flag bits */
#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */
#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */
/* interrupt enable bits */
#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */
#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */
#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */
/* DMA_CHCTL base address */
#define DMA_CHXCTL_BASE (DMA + 0x08U) /*!< the base address of DMA channel CHXCTL register */
#define DMA_CHXCNT_BASE (DMA + 0x0CU) /*!< the base address of DMA channel CHXCNT register */
#define DMA_CHXPADDR_BASE (DMA + 0x10U) /*!< the base address of DMA channel CHXPADDR register */
#define DMA_CHXMADDR_BASE (DMA + 0x14U) /*!< the base address of DMA channel CHXMADDR register */
#define DMA_FLAG_ADD(flag,shift) ((uint32_t)(flag)<<((uint32_t)(shift)*4U)) /*!< DMA channel flag shift */
/* DMA channel shift bit */
#define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + 0x14U*(channel)) /*!< the address of DMA channel CHXCTL register */
#define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + 0x14U*(channel)) /*!< the address of DMA channel CHXCNT register */
#define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + 0x14U*(channel)) /*!< the address of DMA channel CHXPADDR register */
#define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + 0x14U*(channel)) /*!< the address of DMA channel CHXMADDR register */
/* channel priority level */
#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12U)) /*!< DMA channel priority level */
#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */
/* transfer data size of memory */
#define CHCTL_MSIZE(regval) (BITS(10,11) & ((regval) << 10U)) /*!< transfer data size of memory */
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MSIZE(0) /*!< transfer data size of memory is 8-bit */
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MSIZE(1) /*!< transfer data size of memory is 16-bit */
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MSIZE(2) /*!< transfer data size of memory is 32-bit */
/* transfer data size of peripheral */
#define CHCTL_PSIZE(regval) (BITS(8,9) & ((regval) << 8U)) /*!< transfer data size of peripheral */
#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PSIZE(0) /*!< transfer data size of peripheral is 8-bit */
#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PSIZE(1) /*!< transfer data size of peripheral is 16-bit */
#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PSIZE(2) /*!< transfer data size of peripheral is 32-bit */
/* channel data transfer direction */
#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */
#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */
/* peripheral increasing mode */
#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is increasing address mode */
#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is fixed address mode */
/* memory increasing mode */
#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of memory is increasing address mode */
#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of memory is fixed address mode */
/* DMA reset value */
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
#define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000000FU) /*!< clear DMA channel CHXINTFS register */
/* function declarations */
/* deinitialize DMA a channel registers */
void dma_deinit(dma_channel_enum channelx);
/* initialize DMA channel */
void dma_init(dma_channel_enum channelx, dma_parameter_struct init_struct);
/* enable DMA circulation mode */
void dma_circulation_enable(dma_channel_enum channelx);
/* disable DMA circulation mode */
void dma_circulation_disable(dma_channel_enum channelx);
/* enable memory to memory mode */
void dma_memory_to_memory_enable(dma_channel_enum channelx);
/* disable memory to memory mode */
void dma_memory_to_memory_disable(dma_channel_enum channelx);
/* enable DMA channel */
void dma_channel_enable(dma_channel_enum channelx);
/* disable DMA channel */
void dma_channel_disable(dma_channel_enum channelx);
/* set DMA peripheral base address */
void dma_periph_address_config(dma_channel_enum channelx, uint32_t address);
/* set DMA Memory base address */
void dma_memory_address_config(dma_channel_enum channelx, uint32_t address);
/* set the number of remaining data to be transferred by the DMA */
void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number);
/* get the number of remaining data to be transferred by the DMA */
uint32_t dma_transfer_number_get(dma_channel_enum channelx);
/* configure priority level of DMA channel */
void dma_priority_config(dma_channel_enum channelx, uint32_t priority);
/* configure transfer data size of memory */
void dma_memory_width_config (dma_channel_enum channelx, uint32_t msize);
/* configure transfer data size of peripheral */
void dma_periph_width_config (dma_channel_enum channelx, uint32_t psize);
/* enable next address increasement algorithm of memory */
void dma_memory_increase_enable(dma_channel_enum channelx);
/* disable next address increasement algorithm of memory */
void dma_memory_increase_disable(dma_channel_enum channelx);
/* enable next address increasement algorithm of peripheral */
void dma_periph_increase_enable(dma_channel_enum channelx);
/* disable next address increasement algorithm of peripheral */
void dma_periph_increase_disable(dma_channel_enum channelx);
/* configure the direction of data transfer on the channel */
void dma_transfer_direction_config(dma_channel_enum channelx, uint8_t direction);
/* check DMA flag is set or not */
FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag);
/* clear DMA a channel flag */
void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag);
/* enable DMA interrupt */
void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source);
/* disable DMA interrupt */
void dma_interrupt_disable(dma_channel_enum channelx,uint32_t source);
/* check DMA flag is set or not */
FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag);
/* clear DMA a channel flag */
void dma_flag_clear(dma_channel_enum channelx, uint32_t flag);
#endif /* GD32F1X0_DMA_H */

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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_exti.h Normal file
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/*!
\file gd32f1x0_exti.h
\brief definitions for the EXTI
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_EXTI_H
#define GD32F1X0_EXTI_H
#include "gd32f1x0.h"
/* EXTI definitions */
#define EXTI EXTI_BASE
/* registers definitions */
#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */
#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */
#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */
#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */
#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */
#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */
/* bits definitions */
/* EXTI_INTEN */
#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */
#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */
#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */
#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */
#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */
#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */
#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */
#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */
#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */
#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */
#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */
#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */
#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */
#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */
#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */
#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */
#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */
#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */
#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */
#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */
#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */
#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */
#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */
#define EXTI_INTEN_INTEN23 BIT(23) /*!< interrupt from line 23 */
#define EXTI_INTEN_INTEN24 BIT(24) /*!< interrupt from line 24 */
#define EXTI_INTEN_INTEN25 BIT(25) /*!< interrupt from line 25 */
#define EXTI_INTEN_INTEN26 BIT(26) /*!< interrupt from line 26 */
#define EXTI_INTEN_INTEN27 BIT(27) /*!< interrupt from line 27 */
/* EXTI_EVEN */
#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */
#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */
#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */
#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */
#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */
#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */
#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */
#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */
#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */
#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */
#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */
#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */
#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */
#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */
#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */
#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */
#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */
#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */
#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */
#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */
#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */
#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */
#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */
#define EXTI_EVEN_EVEN23 BIT(23) /*!< event from line 23 */
#define EXTI_EVEN_EVEN24 BIT(24) /*!< event from line 24 */
#define EXTI_EVEN_EVEN25 BIT(25) /*!< event from line 25 */
#define EXTI_EVEN_EVEN26 BIT(26) /*!< event from line 26 */
#define EXTI_EVEN_EVEN27 BIT(27) /*!< event from line 27 */
/* EXTI_RTEN */
#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */
#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */
#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */
#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */
#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */
#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */
#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */
#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */
#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */
#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */
#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */
#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */
#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */
#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */
#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */
#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */
#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */
#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */
#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */
#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */
#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */
#define EXTI_RTEN_RTEN22 BIT(22) /*!< rising edge from line 22 */
/* EXTI_FTEN */
#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */
#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */
#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */
#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */
#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */
#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */
#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */
#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */
#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */
#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */
#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */
#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */
#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */
#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */
#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */
#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */
#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */
#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */
#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */
#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */
#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */
#define EXTI_FTEN_FTEN22 BIT(22) /*!< falling edge from line 22 */
/* EXTI_SWIEV */
#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */
#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */
#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */
#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */
/* EXTI_PD */
#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */
#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */
#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */
#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */
#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */
#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */
#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */
#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */
#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */
#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */
#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */
#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */
#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */
#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */
#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */
#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */
#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */
#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */
#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */
#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */
#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */
#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */
/* constants definitions */
/* EXTI line number */
typedef enum
{
EXTI_0 = BIT(0), /*!< EXTI line 0 */
EXTI_1 = BIT(1), /*!< EXTI line 1 */
EXTI_2 = BIT(2), /*!< EXTI line 2 */
EXTI_3 = BIT(3), /*!< EXTI line 3 */
EXTI_4 = BIT(4), /*!< EXTI line 4 */
EXTI_5 = BIT(5), /*!< EXTI line 5 */
EXTI_6 = BIT(6), /*!< EXTI line 6 */
EXTI_7 = BIT(7), /*!< EXTI line 7 */
EXTI_8 = BIT(8), /*!< EXTI line 8 */
EXTI_9 = BIT(9), /*!< EXTI line 9 */
EXTI_10 = BIT(10), /*!< EXTI line 10 */
EXTI_11 = BIT(11), /*!< EXTI line 11 */
EXTI_12 = BIT(12), /*!< EXTI line 12 */
EXTI_13 = BIT(13), /*!< EXTI line 13 */
EXTI_14 = BIT(14), /*!< EXTI line 14 */
EXTI_15 = BIT(15), /*!< EXTI line 15 */
EXTI_16 = BIT(16), /*!< EXTI line 16 */
EXTI_17 = BIT(17), /*!< EXTI line 17 */
#ifdef GD32F130_150
EXTI_18 = BIT(18), /*!< EXTI line 18 */
#endif /* GD32F130_150 */
EXTI_19 = BIT(19), /*!< EXTI line 19 */
EXTI_21 = BIT(21), /*!< EXTI line 21 */
EXTI_22 = BIT(22), /*!< EXTI line 22 */
EXTI_25 = BIT(25), /*!< EXTI line 25 */
EXTI_27 = BIT(27) /*!< EXTI line 27 */
}exti_line_enum;
/* external interrupt and event */
typedef enum
{
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
EXTI_EVENT /*!< EXTI event mode */
}exti_mode_enum;
/* interrupt trigger mode */
typedef enum
{
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */
}exti_trig_type_enum;
/* function declarations */
/* deinitialize the EXTI */
void exti_deinit(void);
/* enable the configuration of EXTI initialize */
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
/* enable the interrupts from EXTI line x */
void exti_interrupt_enable(exti_line_enum linex);
/* enable the events from EXTI line x */
void exti_event_enable(exti_line_enum linex);
/* disable the interrupts from EXTI line x */
void exti_interrupt_disable(exti_line_enum linex);
/* disable the events from EXTI line x */
void exti_event_disable(exti_line_enum linex);
/* get EXTI lines pending flag */
FlagStatus exti_flag_get(exti_line_enum linex);
/* clear EXTI lines pending flag */
void exti_flag_clear(exti_line_enum linex);
/* get EXTI lines flag when the interrupt flag is set */
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
/* clear EXTI lines pending flag */
void exti_interrupt_flag_clear(exti_line_enum linex);
/* EXTI software interrupt event enable */
void exti_software_interrupt_enable(exti_line_enum linex);
/* EXTI software interrupt event disable */
void exti_software_interrupt_disable(exti_line_enum linex);
#endif /* GD32F1X0_EXTI_H */

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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_fmc.h Normal file
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/*!
\file gd32f1x0_fmc.h
\brief definitions for the FMC
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_FMC_H
#define GD32F1X0_FMC_H
#include "gd32f1x0.h"
/* FMC and option byte definition */
#define FMC FMC_BASE /*!< FMC register base address */
#define OB OB_BASE /*!< option byte base address */
/* registers definitions */
#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */
#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */
#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */
#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */
#define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */
#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */
#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC write protection register */
#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */
#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */
#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/
#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */
#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */
/* bits definitions */
/* FMC_WS */
#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
/* FMC_KEY */
#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash unlock key bits */
/* FMC_OBKEY */
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */
/* FMC_STAT */
#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */
#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */
#define FMC_STAT_WPERR BIT(4) /*!< flash write protection error flag bit */
#define FMC_STAT_ENDF BIT(5) /*!< flash end of operation flag bit */
/* FMC_CTL */
#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */
#define FMC_CTL_PER BIT(1) /*!< main flash page erase bit */
#define FMC_CTL_MER BIT(2) /*!< main flash mass erase bit */
#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */
#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */
#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */
#define FMC_CTL_LK BIT(7) /*!< flash lock bit */
#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */
#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
#define FMC_CTL_OBRLD BIT(13) /*!< option bytes reload bit */
/* FMC_ADDR */
#define FMC_ADDR_ADDR BITS(0,31) /*!< flash command address bits */
/* FMC_OBSTAT */
#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit */
#define FMC_OBSTAT_PLVL_BIT0 BIT(1) /*!< protection level bit 0 */
#define FMC_OBSTAT_PLVL_BIT1 BIT(2) /*!< protection level bit 1 */
#define FMC_OBSTAT_USER BITS(8,15) /*!< option bytes user bits */
#define FMC_OBSTAT_DATA BITS(16,31) /*!< option byte data bits */
/* FMC_WSEN */
#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */
#ifdef GD32F170_190
#define FMC_WSEN_BPEN BIT(1) /*!< FMC bit program enable bit */
#endif /* GD32F170_190 */
/* FMC_PID */
#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
/* constants definitions */
/* fmc state */
typedef enum
{
FMC_READY, /*!< the operation has been completed */
FMC_BUSY, /*!< the operation is in progress */
FMC_PGERR, /*!< program error */
FMC_WPERR, /*!< erase/program protection error */
FMC_TOERR, /*!< timeout error */
FMC_OB_HSPC /*!< option byte security protection code high */
}fmc_state_enum;
/* unlock key */
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
/* wait state counter value */
#define WS_WSCNT_0 ((uint8_t)0x00U) /*!< 0 wait state added */
#define WS_WSCNT_1 ((uint8_t)0x01U) /*!< 1 wait state added */
#define WS_WSCNT_2 ((uint8_t)0x02U) /*!< 2 wait state added */
/* read protect configure */
#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */
#define FMC_LSPC ((uint8_t)0xBBU) /*!< low security protection, any value except 0xA5 or 0xCC */
#define FMC_HSPC ((uint8_t)0xCCU) /*!< high security protection */
/* option byte write protection */
#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */
#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */
/* option byte software/hardware free watchdog timer */
#define OBUSER_NWDG_HW(regval) (BIT(0) & ((uint32_t)(regval) << 0))
#define OB_FWDGT_HW OBUSER_NWDG_HW(0) /*!< hardware free watchdog timer */
#define OB_FWDGT_SW OBUSER_NWDG_HW(1) /*!< software free watchdog timer */
/* option byte reset or not entering deep sleep mode */
#define OBUSER_NRST_DPSLP(regval) (BIT(1) & ((uint32_t)(regval) << 1))
#define OB_DEEPSLEEP_RST OBUSER_NRST_DPSLP(0) /*!< generate a reset instead of entering deepsleep mode */
#define OB_DEEPSLEEP_NRST OBUSER_NRST_DPSLP(1) /*!< no reset when entering deepsleep mode */
/* option byte reset or not entering standby mode */
#define OBUSER_NRST_STDBY(regval) (BIT(2) & ((uint32_t)(regval) << 2))
#define OB_STDBY_RST OBUSER_NRST_STDBY(0) /*!< generate a reset instead of entering standby mode */
#define OB_STDBY_NRST OBUSER_NRST_STDBY(1) /*!< no reset when entering deepsleep mode */
/* option byte OB_BOOT1_n set */
#define OBUSER_BOOT1_N(regval) (BIT(4) & ((uint32_t)(regval) << 4))
#define OB_BOOT1_SET_1 OBUSER_BOOT1_N(0) /*!< BOOT1 bit is 1 */
#define OB_BOOT1_SET_0 OBUSER_BOOT1_N(1) /*!< BOOT1 bit is 0 */
/* option byte VDDA monitor enable/disable */
#define OBUSER_VDDA_VISOR(regval) (BIT(5) & ((uint32_t)(regval) << 5))
#define OB_VDDA_DISABLE OBUSER_VDDA_VISOR(0) /*!< disable VDDA monitor */
#define OB_VDDA_ENABLE OBUSER_VDDA_VISOR(1) /*!< enable VDDA monitor */
/* option byte SRAM parity enable/disable */
#define OBUSER_SRAM_PARITY(regval) (BIT(6) & ((uint32_t)(regval) << 6))
#define OB_SRAM_PARITY_ENABLE OBUSER_SRAM_PARITY(0) /*!< enable SRAM parity check */
#define OB_SRAM_PARITY_DISABLE OBUSER_SRAM_PARITY(1) /*!< disable SRAM parity check */
/* option byte security protection level in FMC_OBSTAT register */
#define OB_OBSTAT_PLEVEL_NO ((uint32_t)0x00000000U) /*!< no security protection */
#define OB_OBSTAT_PLEVEL_LOW ((uint32_t)0x00000002U) /*!< low security protection */
#define OB_OBSTAT_PLEVEL_HIGH ((uint32_t)0x00000006U) /*!< high security protection */
/* option byte user mask */
#define OB_USER_MASK ((uint8_t)0x88U) /*!< OB_USER reserved bit mask */
/* option byte data address */
#define OB_DATA_ADDR0 ((uint32_t)0x1FFFF804U) /*!< option byte data address 0 */
#define OB_DATA_ADDR1 ((uint32_t)0x1FFFF806U) /*!< option byte data address 1 */
/* FMC flags */
#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */
#define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */
#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */
#define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */
/* FMC interrupt enable */
#define FMC_INTEN_END FMC_CTL_ENDIE /*!< enable FMC end of operation interrupt */
#define FMC_INTEN_ERR FMC_CTL_ERRIE /*!< enable FMC error interrupt */
/* FMC time out */
#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< count to judge of FMC timeout */
/* function declarations */
/* FMC main memory programming functions */
/* unlock the main FMC operation */
void fmc_unlock(void);
/* lock the main FMC operation */
void fmc_lock(void);
/* set the wait state counter value */
void fmc_wscnt_set(uint8_t wscnt);
/* fmc wait state enable */
void fmc_wait_state_enable(void);
/* fmc wait state disable */
void fmc_wait_state_disable(void);
/* FMC erase page */
fmc_state_enum fmc_page_erase(uint32_t page_address);
/* FMC erase whole chip */
fmc_state_enum fmc_mass_erase(void);
/* FMC program a word at the corresponding address */
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
/* FMC program a half word at the corresponding address */
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
#ifdef GD32F170_190
/* FMC program a word at the corresponding address without erasing */
fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data);
#endif /* GD32F170_190 */
/* FMC option bytes programming functions */
/* unlock the option byte operation */
void ob_unlock(void);
/* lock the option byte operation */
void ob_lock(void);
/* reload the option byte and generate a system reset */
void ob_reset(void);
/* erase option byte */
fmc_state_enum ob_erase(void);
/* enable option byte write protection (OB_WP) */
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
/* configure read out protect */
fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
/* write the FMC option byte user */
fmc_state_enum ob_user_write(uint8_t ob_user);
/* write the FMC option byte data */
fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
/* get the FMC option byte OB_USER */
uint8_t ob_user_get(void);
/* get the FMC option byte OB_DATA */
uint16_t ob_data_get(void);
/* get the FMC option byte write protection */
uint16_t ob_write_protection_get(void);
/* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */
uint32_t ob_obstat_plevel_get(void);
/* FMC interrupts and flags management functions */
/* enable FMC interrupt */
void fmc_interrupt_enable(uint32_t interrupt);
/* disable FMC interrupt */
void fmc_interrupt_disable(uint32_t interrupt);
/* get flag set or reset */
FlagStatus fmc_flag_get(uint32_t flag);
/* clear the FMC pending flag */
void fmc_flag_clear(uint32_t flag);
/* return the FMC state */
fmc_state_enum fmc_state_get(void);
/* check FMC ready or not */
fmc_state_enum fmc_ready_wait(uint32_t timeout);
#endif /* GD32F1X0_FMC_H */

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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_fwdgt.h Normal file
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/*!
\file gd32f1x0_fwdgt.h
\brief definitions for the FWDGT
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_FWDGT_H
#define GD32F1X0_FWDGT_H
#include "gd32f1x0.h"
/* FWDGT definitions */
#define FWDGT FWDGT_BASE
/* registers definitions */
#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */
#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */
#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */
#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */
#define FWDGT_WND REG32((FWDGT) + 0x10U) /*!< FWDGT window register */
/* bits definitions */
/* FWDGT_CTL */
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
/* FWDGT_PSC */
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
/* FWDGT_RLD */
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
/* FWDGT_STAT */
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */
/* FWDGT_WND */
#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */
/* constants definitions */
/* ctl register value */
#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_CTL_CMD bit field */
/* psc register value */
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U))
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
/* rld register value */
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_RLD_RLD bit field */
/* wnd register value */
#define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_WND_WND bit field */
/* control value */
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
/* FWDGT timeout value */
#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
/* FWDGT flag definitions */
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */
#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */
/* function declarations */
/* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */
void fwdgt_write_disable(void);
/* start the free watchdog timer counter */
void fwdgt_enable(void);
/* configure the free watchdog timer counter window value */
ErrStatus fwdgt_window_value_config(uint16_t window_value);
/* reload the counter of FWDGT */
void fwdgt_counter_reload(void);
/* configure counter reload value, and prescaler divider value */
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
/* get flag state of FWDGT */
FlagStatus fwdgt_flag_get(uint16_t flag);
#endif /* GD32F1X0_FWDGT_H */

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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_gpio.h Normal file
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/*!
\file gd32f1x0_gpio.h
\brief definitions for the GPIO
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform for GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform for GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_GPIO_H
#define GD32F1X0_GPIO_H
#include "gd32f1x0.h"
/* GPIOx(x=A,B,C,D,F) definitions */
#define GPIOA (GPIO_BASE + 0x00000000U)
#define GPIOB (GPIO_BASE + 0x00000400U)
#define GPIOC (GPIO_BASE + 0x00000800U)
#define GPIOD (GPIO_BASE + 0x00000C00U)
#define GPIOF (GPIO_BASE + 0x00001400U)
/* registers definitions */
#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register */
#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port output mode register */
#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port output speed register */
#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/down register */
#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */
#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */
#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operation register */
#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */
#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */
#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */
#define GPIO_BC(gpiox) REG32((gpiox) + 0x28U) /*!< GPIO bit clear register */
#define GPIO_TG(gpiox) REG32((gpiox) + 0x2CU) /*!< GPIO port bit toggle register */
/* bits definitions */
/* GPIO_CTL */
#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */
#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */
#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */
#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */
#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */
#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */
#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */
#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */
#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */
#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */
#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */
#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */
#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */
#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */
#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */
#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */
/* GPIO_OMODE */
#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */
#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */
#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */
#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */
#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */
#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */
#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */
#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */
#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */
#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */
#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */
#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */
#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */
#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */
#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */
#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */
/* GPIO_OSPD */
#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */
#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */
#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */
#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */
#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */
#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */
#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */
#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */
#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */
#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */
#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */
#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */
#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */
#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */
#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */
#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */
/* GPIO_PUD */
#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */
#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */
#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */
#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */
#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */
#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */
#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */
#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */
#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */
#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */
#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */
#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */
#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */
#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */
#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */
#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */
/* GPIO_ISTAT */
#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */
#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */
#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */
#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */
#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */
#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */
#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */
#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */
#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */
#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */
#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */
#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */
#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */
#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */
#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */
#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */
/* GPIO_OCTL */
#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */
#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */
#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */
#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */
#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */
#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */
#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */
#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */
#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */
#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */
#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */
#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */
#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */
#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */
#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */
#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */
/* GPIO_BOP */
#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */
#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */
#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */
#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */
#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */
#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */
#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */
#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */
#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */
#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */
#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */
#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */
#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */
#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */
#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */
#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */
#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */
#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */
#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */
#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */
#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */
#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */
#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */
#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */
#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */
#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */
#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */
#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */
#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */
#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */
#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */
/* GPIO_LOCK */
#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */
#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */
#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */
#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */
#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */
#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */
#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */
#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */
#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */
#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */
#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */
#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */
#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */
#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */
#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */
#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */
#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */
/* GPIO_AFSEL0 */
#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */
#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */
#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */
#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */
#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */
#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */
#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */
#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */
/* GPIO_AFSEL1 */
#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */
#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */
#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */
#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */
#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */
#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */
#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */
#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */
/* GPIO_BC */
#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */
#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */
#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */
#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */
#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */
#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */
#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */
#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */
#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */
#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */
#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */
#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */
#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */
#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */
#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */
#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */
#ifdef GD32F170_190
/* GPIO_TG */
#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */
#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */
#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */
#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */
#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */
#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */
#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */
#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */
#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */
#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */
#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */
#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */
#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */
#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */
#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */
#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */
#endif /* GD32F170_190 */
/* constants definitions */
typedef FlagStatus bit_status;
/* output mode definitions */
#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */
#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */
#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */
#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */
/* pull-up/pull-down definitions */
#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< without weak pull-up and pull-down resistors */
#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with weak pull-up resistor */
#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with weak pull-down resistor */
/* GPIO pin definitions */
#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */
#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */
#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */
#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */
#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */
#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */
#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */
#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */
#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */
#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */
#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */
#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */
#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */
#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */
#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */
#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */
#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */
/* GPIO mode configuration values */
#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n))))
#define GPIO_MODE_MASK(n) (0x3U << (2U * (n)))
/* GPIO pull-up/pull-down values */
#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n))))
#define GPIO_PUPD_MASK(n) (0x3U << (2U * (n)))
/* GPIO output speed values */
#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n))))
#define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n)))
/* GPIO output type */
#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */
#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */
/* GPIO output max speed value */
#define OSPD_OSPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define GPIO_OSPEED_2MHZ OSPD_OSPD(0) /*!< output max speed 2M */
#define GPIO_OSPEED_10MHZ OSPD_OSPD(1) /*!< output max speed 10M */
#define GPIO_OSPEED_50MHZ OSPD_OSPD(3) /*!< output max speed 50M */
/* GPIO alternate function values */
#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
#define GPIO_AFR_MASK(n) (0xFU << (4U * (n)))
/* GPIO alternate function */
#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
#define GPIO_AF_0 AF(0) /*!< alternate function selected 0 */
#define GPIO_AF_1 AF(1) /*!< alternate function selected 1 */
#define GPIO_AF_2 AF(2) /*!< alternate function selected 2 */
#define GPIO_AF_3 AF(3) /*!< alternate function selected 3 */
#define GPIO_AF_4 AF(4) /*!< alternate function selected 4 */
#define GPIO_AF_5 AF(5) /*!< alternate function selected 5 */
#define GPIO_AF_6 AF(6) /*!< alternate function selected 6 */
#define GPIO_AF_7 AF(7) /*!< alternate function selected 7 */
#define GPIO_AF_8 AF(8) /*!< alternate function selected 8 */
#define GPIO_AF_9 AF(9) /*!< alternate function selected 9 */
#define GPIO_AF_10 AF(10) /*!< alternate function selected 10 */
#define GPIO_AF_11 AF(11) /*!< alternate function selected 11 */
/* function declarations */
/* reset GPIO port */
void gpio_deinit(uint32_t gpio_periph);
/* set GPIO mode */
void gpio_mode_set(uint32_t gpio_periph,uint32_t mode,uint32_t pull_up_down,uint32_t pin);
/* set GPIO output type and speed */
void gpio_output_options_set(uint32_t gpio_periph,uint8_t otype,uint32_t speed,uint32_t pin);
/* set GPIO pin bit */
void gpio_bit_set(uint32_t gpio_periph,uint32_t pin);
/* reset GPIO pin bit */
void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin);
/* write data to the specified GPIO pin */
void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value);
/* write data to the specified GPIO port */
void gpio_port_write(uint32_t gpio_periph,uint16_t data);
/* get GPIO pin input status */
FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin);
/* get GPIO port input status */
uint16_t gpio_input_port_get(uint32_t gpio_periph);
/* get GPIO pin output status */
FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin);
/* get GPIO port output status */
uint16_t gpio_output_port_get(uint32_t gpio_periph);
/* set GPIO alternate function */
void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num,uint32_t pin);
/* lock GPIO pin bit */
void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin);
#ifdef GD32F170_190
/* toggle GPIO pin status */
void gpio_bit_toggle(uint32_t gpio_periph,uint32_t pin);
/* toggle GPIO port status */
void gpio_port_toggle(uint32_t gpio_periph);
#endif /* GD32F170_190 */
#endif /* GD32F1X0_GPIO_H */

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/*!
\file gd32f1x0_i2c.h
\brief definitions for the I2C
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_I2C_H
#define GD32F1X0_I2C_H
#include "gd32f1x0.h"
/* I2Cx(x=0,1) definitions */
#define I2C0 I2C_BASE /*!< I2C0 base address */
#define I2C1 (I2C_BASE+0x400U) /*!< I2C1 base address */
#ifdef GD32F170_190
#define I2C2 (I2C_BASE+0x6C00U) /*!< I2C2 base address */
#endif /* GD32F170_190 */
/* registers definitions */
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */
#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */
#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */
#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */
#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */
#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */
#ifdef GD32F170_190
#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x80U) /*!< I2C SAM control and status register */
#endif /* GD32F170_190 */
/* bits definitions */
/* I2Cx_CTL0 */
#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */
#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */
#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */
#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */
#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */
#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */
#define I2C_CTL0_DISSTRC BIT(7) /*!< clock stretching disable (slave mode) */
#define I2C_CTL0_START BIT(8) /*!< start generation */
#define I2C_CTL0_STOP BIT(9) /*!< stop generation */
#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */
#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */
#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */
#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */
#define I2C_CTL0_SRESET BIT(15) /*!< software reset */
/* I2Cx_CTL1 */
#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */
#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */
#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */
#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */
#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */
#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */
/* I2Cx_SADDR0 */
#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
/* I2Cx_SADDR1 */
#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */
/* I2Cx_DATA */
#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */
/* I2Cx_STAT0 */
#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */
#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */
#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */
#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */
#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */
#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */
#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */
#define I2C_STAT0_BERR BIT(8) /*!< bus error */
#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */
#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */
#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */
#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */
#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */
#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */
/* I2Cx_STAT1 */
#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */
#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */
#define I2C_STAT1_TRS BIT(2) /*!< transmitter/receiver */
#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */
#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */
#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */
#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */
#define I2C_STAT1_ECV BITS(8,15) /*!< packet error checking value */
/* I2Cx_CKCFG */
#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */
#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */
#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */
/* I2Cx_RT */
#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */
#ifdef GD32F170_190
/* I2Cx_SAMCS */
#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */
#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */
#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */
#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */
#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */
#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */
#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */
#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */
#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag, cleared by software write 0 */
#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag, cleared by software write 0 */
#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag, cleared by software write 0 */
#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag, cleared by software write 0 */
#endif /* GD32F170_190 */
/* constants definitions */
/* SMBus/I2C mode switch and SMBus type selection */
#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
/* SMBus/I2C mode switch and SMBus type selection */
#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */
#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */
/* I2C transfer direction */
#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */
#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */
/* whether or not to send an ACK */
#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */
/* I2C POAP position*/
#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */
#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
/* I2C dual-address mode switch */
#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */
#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */
/* whether or not to stretch SCL low */
#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */
#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC /*!< SCL stretching is disabled */
/* whether or not to response to a general call */
#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */
#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */
/* software reset I2C */
#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
/* I2C DMA mode configure */
/* DMA mode switch */
#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */
#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */
/* flag indicating DMA last transfer */
#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
/* I2C PEC configure */
/* PEC enable */
#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
/* PEC transfer */
#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */
#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
/* I2C SMBus configure */
/* issue or not alert through SMBA pin */
#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
/* ARP protocol in SMBus switch */
#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */
#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */
/* fast mode plus enable */
#define I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN /*!< fast mode plus enable */
#define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */
/* transmit I2C data */
#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
/* receive I2C data */
#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
/* I2C flag definitions */
#define I2C_FLAG_SBSEND BIT(0) /*!< start condition sent out in master mode */
#define I2C_FLAG_ADDSEND BIT(1) /*!< address is sent in master mode or received and matches in slave mode */
#define I2C_FLAG_BTC BIT(2) /*!< byte transmission finishes */
#define I2C_FLAG_ADD10SEND BIT(3) /*!< header of 10-bit address is sent in master mode */
#define I2C_FLAG_STPDET BIT(4) /*!< etop condition detected in slave mode */
#define I2C_FLAG_RBNE BIT(6) /*!< I2C_DATA is not Empty during receiving */
#define I2C_FLAG_TBE BIT(7) /*!< I2C_DATA is empty during transmitting */
#define I2C_FLAG_BERR BIT(8) /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
#define I2C_FLAG_LOSTARB BIT(9) /*!< arbitration lost in master mode */
#define I2C_FLAG_AERR BIT(10) /*!< acknowledge error */
#define I2C_FLAG_OUERR BIT(11) /*!< over-run or under-run situation occurs in slave mode */
#define I2C_FLAG_PECERR BIT(12) /*!< PEC error when receiving data */
#define I2C_FLAG_SMBTO BIT(14) /*!< timeout signal in SMBus mode */
#define I2C_FLAG_SMBALT BIT(15) /*!< SMBus alert status */
#define I2C_FLAG_MASTER (BIT(0)|BIT(31)) /*!< a flag indicating whether I2C block is in master or slave mode */
#define I2C_FLAG_I2CBSY (BIT(1)|BIT(31)) /*!< busy flag */
#define I2C_FLAG_TRS (BIT(2)|BIT(31)) /*!< whether the I2C is a transmitter or a receiver */
#define I2C_FLAG_RXGC (BIT(4)|BIT(31)) /*!< general call address (00h) received */
#define I2C_FLAG_DEFSMB (BIT(5)|BIT(31)) /*!< default address of SMBus device */
#define I2C_FLAG_HSTSMB (BIT(6)|BIT(31)) /*!< SMBus host header detected in slave mode */
#define I2C_FLAG_DUMOD (BIT(7)|BIT(31)) /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
/* I2C interrupt flags */
#define I2C_INT_FLAG_SBSEND I2C_FLAG_SBSEND /*!< start condition sent out in master mode interrupt flag */
#define I2C_INT_FLAG_ADDSEND I2C_FLAG_ADDSEND /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
#define I2C_INT_FLAG_BTC I2C_FLAG_BTC /*!< byte transmission finishes */
#define I2C_INT_FLAG_ADD10SEND I2C_FLAG_ADD10SEND /*!< header of 10-bit address is sent in master mode interrupt flag */
#define I2C_INT_FLAG_STPDET I2C_FLAG_STPDET /*!< stop condition detected in slave mode interrupt flag */
#define I2C_INT_FLAG_RBNE I2C_FLAG_RBNE /*!< I2C_DATA is not Empty during receiving interrupt flag */
#define I2C_INT_FLAG_TBE I2C_FLAG_TBE /*!< I2C_DATA is empty during transmitting interrupt flag */
#define I2C_INT_FLAG_BERR I2C_FLAG_BERR /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
#define I2C_INT_FLAG_LOSTARB I2C_FLAG_LOSTARB /*!< arbitration lost in master mode interrupt flag */
#define I2C_INT_FLAG_AERR I2C_FLAG_AERR /*!< acknowledge error interrupt flag */
#define I2C_INT_FLAG_OUERR I2C_FLAG_OUERR /*!< over-run or under-run situation occurs in slave mode interrupt flag */
#define I2C_INT_FLAG_PECERR I2C_FLAG_PECERR /*!< PEC error when receiving data interrupt flag */
#define I2C_INT_FLAG_SMBTO I2C_FLAG_SMBTO /*!< timeout signal in SMBus mode interrupt flag */
#define I2C_INT_FLAG_SMBALT I2C_FLAG_SMBALT /*!< SMBus Alert status interrupt flag */
/* I2C interrupt enable bit */
#define I2C_INT_ERR I2C_CTL1_ERRIE /*!< error interrupt enable */
#define I2C_INT_EV I2C_CTL1_EVIE /*!< event interrupt enable */
#define I2C_INT_BUF I2C_CTL1_BUFIE /*!< buffer interrupt enable */
/* I2C duty cycle in fast mode */
#define CKCFG_DTCY(regval) (BIT(14) & ((uint32_t)(regval) << 14))
#define I2C_DTCY_2 CKCFG_DTCY(0) /*!< I2C fast mode Tlow/Thigh = 2 */
#define I2C_DTCY_16_9 CKCFG_DTCY(1) /*!< I2C fast mode Tlow/Thigh = 16/9 */
/* address mode for the I2C slave */
#define SADDR0_ADDFORMAT(regval) (BIT(15) & ((uint32_t)(regval) << 15))
#define I2C_ADDFORMAT_7BITS SADDR0_ADDFORMAT(0) /*!< address:7 bits */
#define I2C_ADDFORMAT_10BITS SADDR0_ADDFORMAT(1) /*!< address:10 bits */
/* function declarations */
/* reset I2C */
void i2c_deinit(uint32_t i2c_periph);
/* configure I2C clock */
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
/* configure I2C address */
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
/* SMBus type selection */
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
/* whether or not to send an ACK */
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
/* configure I2C POAP position */
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
/* master send slave address */
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
/* dual-address mode switch */
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr);
/* enable I2C */
void i2c_enable(uint32_t i2c_periph);
/* disable I2C */
void i2c_disable(uint32_t i2c_periph);
/* generate a START condition on I2C bus */
void i2c_start_on_bus(uint32_t i2c_periph);
/* generate a STOP condition on I2C bus */
void i2c_stop_on_bus(uint32_t i2c_periph);
/* I2C transmit data function */
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
/* I2C receive data function */
uint8_t i2c_data_receive(uint32_t i2c_periph);
/* I2C DMA mode enable */
void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate);
/* flag indicating DMA last transfer */
void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast);
/* whether to stretch SCL low when data is not ready in slave mode */
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara );
/* whether or not to response to a general call */
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
/* software reset I2C */
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
/* check I2C flag is set or not */
FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag);
/* clear I2C flag */
void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag);
/* enable I2C interrupt */
void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype);
/* disable I2C interrupt */
void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype);
/* check I2C interrupt flag */
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,uint32_t intflag);
/* clear I2C interrupt flag */
void i2c_interrupt_flag_clear(uint32_t i2c_periph,uint32_t intflag);
/* I2C PEC calculation on or off */
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate);
/* I2C whether to transfer PEC value */
void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara);
/* packet error checking value */
uint8_t i2c_pec_value_get(uint32_t i2c_periph);
/* I2C issue alert through SMBA pin */
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara);
/* I2C ARP protocol in SMBus switch */
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate);
#ifdef GD32F170_190
/* enable SAM_V interface */
void i2c_sam_enable(uint32_t i2c_periph);
/* disable SAM_V interface */
void i2c_sam_disable(uint32_t i2c_periph);
/* enable SAM_V interface timeout detect */
void i2c_sam_timeout_enable(uint32_t i2c_periph);
/* disable SAM_V interface timeout detect */
void i2c_sam_timeout_disable(uint32_t i2c_periph);
/* enable the specified I2C SAM interrupt */
void i2c_sam_interrupt_enable(uint32_t i2c_periph, uint32_t inttype);
/* disable the specified I2C SAM interrupt */
void i2c_sam_interrupt_disable(uint32_t i2c_periph, uint32_t inttype);
/* check i2c SAM state */
FlagStatus i2c_sam_flag_get(uint32_t i2c_periph, uint32_t samstate);
/* clear i2c SAM state */
void i2c_sam_flag_clear(uint32_t i2c_periph, uint32_t samstate);
#endif /*GD32F170_190*/
#endif /* GD32F1X0_I2C_H */

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/*!
\file gd32f1x0_ivref.h
\brief definitions for the IVREF
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifdef GD32F170_190
#ifndef GD32F1X0_IVREF_H
#define GD32F1X0_IVREF_H
#include "gd32f1x0.h"
/* IVREF definitions */
#define IVREF IVREF_BASE
/* registers definitions */
#define IVREF_CTL REG32(IVREF + 0x300U) /*!< IVREF control register */
/* bits definitions */
/* IVREF_CTL */
#define IVREF_CTL_CSDT BITS(0,5) /*!< current step data */
#define IVREF_CTL_SCMOD BIT(7) /*!< sink current mode */
#define IVREF_CTL_CPT BITS(8,12) /*!< current precision trim */
#define IVREF_CTL_SSEL BIT(14) /*!< step selection */
#define IVREF_CTL_CREN BIT(15) /*!< current reference enable */
#define IVREF_CTL_VPT BITS(24,28) /*!< voltage precision trim */
#define IVREF_CTL_DECAP BIT(30) /*!< connect/disconnect external capacitor */
#define IVREF_CTL_VREN BIT(31) /*!< voltage reference enable */
/* constants definitions */
/* vref mode selection */
#define VREF_DISCONNECT_EXTERNAL_CAP BIT(30) /*!< VREF disconnect external capacitor */
#define VREF_CONNECT_EXTERNAL_CAP ((uint32_t)0x00000000) /*!< VREF connect external capacitor */
/* vref voltage precision trim */
#define CTL_VPT(regval) (BITS(24,28) & ((regval) << 24))
#define VREF_VOLT_PRECISION_TRIM_0 CTL_VPT(0) /*!< VREF voltage precision trim 0 */
#define VREF_VOLT_PRECISION_TRIM_1 CTL_VPT(1) /*!< VREF voltage precision trim 1 */
#define VREF_VOLT_PRECISION_TRIM_2 CTL_VPT(2) /*!< VREF voltage precision trim 2 */
#define VREF_VOLT_PRECISION_TRIM_3 CTL_VPT(3) /*!< VREF voltage precision trim 3 */
#define VREF_VOLT_PRECISION_TRIM_4 CTL_VPT(4) /*!< VREF voltage precision trim 4 */
#define VREF_VOLT_PRECISION_TRIM_5 CTL_VPT(5) /*!< VREF voltage precision trim 5 */
#define VREF_VOLT_PRECISION_TRIM_6 CTL_VPT(6) /*!< VREF voltage precision trim 6 */
#define VREF_VOLT_PRECISION_TRIM_7 CTL_VPT(7) /*!< VREF voltage precision trim 7 */
#define VREF_VOLT_PRECISION_TRIM_8 CTL_VPT(8) /*!< VREF voltage precision trim 8 */
#define VREF_VOLT_PRECISION_TRIM_9 CTL_VPT(9) /*!< VREF voltage precision trim 9 */
#define VREF_VOLT_PRECISION_TRIM_10 CTL_VPT(10) /*!< VREF voltage precision trim 10 */
#define VREF_VOLT_PRECISION_TRIM_11 CTL_VPT(11) /*!< VREF voltage precision trim 11 */
#define VREF_VOLT_PRECISION_TRIM_12 CTL_VPT(12) /*!< VREF voltage precision trim 12 */
#define VREF_VOLT_PRECISION_TRIM_13 CTL_VPT(13) /*!< VREF voltage precision trim 13 */
#define VREF_VOLT_PRECISION_TRIM_14 CTL_VPT(14) /*!< VREF voltage precision trim 14 */
#define VREF_VOLT_PRECISION_TRIM_15 CTL_VPT(15) /*!< VREF voltage precision trim 15 */
#define VREF_VOLT_PRECISION_TRIM_16 CTL_VPT(16) /*!< VREF voltage precision trim 16 */
#define VREF_VOLT_PRECISION_TRIM_17 CTL_VPT(17) /*!< VREF voltage precision trim 17 */
#define VREF_VOLT_PRECISION_TRIM_18 CTL_VPT(18) /*!< VREF voltage precision trim 18 */
#define VREF_VOLT_PRECISION_TRIM_19 CTL_VPT(19) /*!< VREF voltage precision trim 19 */
#define VREF_VOLT_PRECISION_TRIM_20 CTL_VPT(20) /*!< VREF voltage precision trim 20 */
#define VREF_VOLT_PRECISION_TRIM_21 CTL_VPT(21) /*!< VREF voltage precision trim 21 */
#define VREF_VOLT_PRECISION_TRIM_22 CTL_VPT(22) /*!< VREF voltage precision trim 22 */
#define VREF_VOLT_PRECISION_TRIM_23 CTL_VPT(23) /*!< VREF voltage precision trim 23 */
#define VREF_VOLT_PRECISION_TRIM_24 CTL_VPT(24) /*!< VREF voltage precision trim 24 */
#define VREF_VOLT_PRECISION_TRIM_25 CTL_VPT(25) /*!< VREF voltage precision trim 25 */
#define VREF_VOLT_PRECISION_TRIM_26 CTL_VPT(26) /*!< VREF voltage precision trim 26 */
#define VREF_VOLT_PRECISION_TRIM_27 CTL_VPT(27) /*!< VREF voltage precision trim 27 */
#define VREF_VOLT_PRECISION_TRIM_28 CTL_VPT(28) /*!< VREF voltage precision trim 28 */
#define VREF_VOLT_PRECISION_TRIM_29 CTL_VPT(29) /*!< VREF voltage precision trim 29 */
#define VREF_VOLT_PRECISION_TRIM_30 CTL_VPT(30) /*!< VREF voltage precision trim 30 */
#define VREF_VOLT_PRECISION_TRIM_31 CTL_VPT(31) /*!< VREF voltage precision trim 31 */
/* iref current precision trim */
#define CTL_CPT(regval) (BITS(8,12) & ((regval) << 8))
#define IREF_CUR_PRECISION_TRIM_0 CTL_CPT(0) /*!< IREF current precision trim 0 */
#define IREF_CUR_PRECISION_TRIM_1 CTL_CPT(1) /*!< IREF current precision trim 1 */
#define IREF_CUR_PRECISION_TRIM_2 CTL_CPT(2) /*!< IREF current precision trim 2 */
#define IREF_CUR_PRECISION_TRIM_3 CTL_CPT(3) /*!< IREF current precision trim 3 */
#define IREF_CUR_PRECISION_TRIM_4 CTL_CPT(4) /*!< IREF current precision trim 4 */
#define IREF_CUR_PRECISION_TRIM_5 CTL_CPT(5) /*!< IREF current precision trim 5 */
#define IREF_CUR_PRECISION_TRIM_6 CTL_CPT(6) /*!< IREF current precision trim 6 */
#define IREF_CUR_PRECISION_TRIM_7 CTL_CPT(7) /*!< IREF current precision trim 7 */
#define IREF_CUR_PRECISION_TRIM_8 CTL_CPT(8) /*!< IREF current precision trim 8 */
#define IREF_CUR_PRECISION_TRIM_9 CTL_CPT(9) /*!< IREF current precision trim 9 */
#define IREF_CUR_PRECISION_TRIM_10 CTL_CPT(10) /*!< IREF current precision trim 10 */
#define IREF_CUR_PRECISION_TRIM_11 CTL_CPT(11) /*!< IREF current precision trim 11 */
#define IREF_CUR_PRECISION_TRIM_12 CTL_CPT(12) /*!< IREF current precision trim 12 */
#define IREF_CUR_PRECISION_TRIM_13 CTL_CPT(13) /*!< IREF current precision trim 13 */
#define IREF_CUR_PRECISION_TRIM_14 CTL_CPT(14) /*!< IREF current precision trim 14 */
#define IREF_CUR_PRECISION_TRIM_15 CTL_CPT(15) /*!< IREF current precision trim 15 */
#define IREF_CUR_PRECISION_TRIM_16 CTL_CPT(16) /*!< IREF current precision trim 16 */
#define IREF_CUR_PRECISION_TRIM_17 CTL_CPT(17) /*!< IREF current precision trim 17 */
#define IREF_CUR_PRECISION_TRIM_18 CTL_CPT(18) /*!< IREF current precision trim 18 */
#define IREF_CUR_PRECISION_TRIM_19 CTL_CPT(19) /*!< IREF current precision trim 19 */
#define IREF_CUR_PRECISION_TRIM_20 CTL_CPT(20) /*!< IREF current precision trim 20 */
#define IREF_CUR_PRECISION_TRIM_21 CTL_CPT(21) /*!< IREF current precision trim 21 */
#define IREF_CUR_PRECISION_TRIM_22 CTL_CPT(22) /*!< IREF current precision trim 22 */
#define IREF_CUR_PRECISION_TRIM_23 CTL_CPT(23) /*!< IREF current precision trim 23 */
#define IREF_CUR_PRECISION_TRIM_24 CTL_CPT(24) /*!< IREF current precision trim 24 */
#define IREF_CUR_PRECISION_TRIM_25 CTL_CPT(25) /*!< IREF current precision trim 25 */
#define IREF_CUR_PRECISION_TRIM_26 CTL_CPT(26) /*!< IREF current precision trim 26 */
#define IREF_CUR_PRECISION_TRIM_27 CTL_CPT(27) /*!< IREF current precision trim 27 */
#define IREF_CUR_PRECISION_TRIM_28 CTL_CPT(28) /*!< IREF current precision trim 28 */
#define IREF_CUR_PRECISION_TRIM_29 CTL_CPT(29) /*!< IREF current precision trim 29 */
#define IREF_CUR_PRECISION_TRIM_30 CTL_CPT(30) /*!< IREF current precision trim 30 */
#define IREF_CUR_PRECISION_TRIM_31 CTL_CPT(31) /*!< IREF current precision trim 31 */
/* iref mode selection */
#define IREF_MODE_LOW_POWER ((uint32_t)0x00000000)
#define IREF_MODE_HIGH_CURRENT BIT(14)
/* iref current step */
#define CTL_CSDA(regval) (BITS(0,5) & ((regval) << 5))
#define IREF_CUR_STEP_DATA_0 CTL_CSDA(0) /*!< IREF current step data 0 */
#define IREF_CUR_STEP_DATA_1 CTL_CSDA(1) /*!< IREF current step data 1 */
#define IREF_CUR_STEP_DATA_2 CTL_CSDA(2) /*!< IREF current step data 2 */
#define IREF_CUR_STEP_DATA_3 CTL_CSDA(3) /*!< IREF current step data 3 */
#define IREF_CUR_STEP_DATA_4 CTL_CSDA(4) /*!< IREF current step data 4 */
#define IREF_CUR_STEP_DATA_5 CTL_CSDA(5) /*!< IREF current step data 5 */
#define IREF_CUR_STEP_DATA_6 CTL_CSDA(6) /*!< IREF current step data 6 */
#define IREF_CUR_STEP_DATA_7 CTL_CSDA(7) /*!< IREF current step data 7 */
#define IREF_CUR_STEP_DATA_8 CTL_CSDA(8) /*!< IREF current step data 8 */
#define IREF_CUR_STEP_DATA_9 CTL_CSDA(9) /*!< IREF current step data 9 */
#define IREF_CUR_STEP_DATA_10 CTL_CSDA(10) /*!< IREF current step data 10 */
#define IREF_CUR_STEP_DATA_11 CTL_CSDA(11) /*!< IREF current step data 11 */
#define IREF_CUR_STEP_DATA_12 CTL_CSDA(12) /*!< IREF current step data 12 */
#define IREF_CUR_STEP_DATA_13 CTL_CSDA(13) /*!< IREF current step data 13 */
#define IREF_CUR_STEP_DATA_14 CTL_CSDA(14) /*!< IREF current step data 14 */
#define IREF_CUR_STEP_DATA_15 CTL_CSDA(15) /*!< IREF current step data 15 */
#define IREF_CUR_STEP_DATA_16 CTL_CSDA(16) /*!< IREF current step data 16 */
#define IREF_CUR_STEP_DATA_17 CTL_CSDA(17) /*!< IREF current step data 17 */
#define IREF_CUR_STEP_DATA_18 CTL_CSDA(18) /*!< IREF current step data 18 */
#define IREF_CUR_STEP_DATA_19 CTL_CSDA(19) /*!< IREF current step data 19 */
#define IREF_CUR_STEP_DATA_20 CTL_CSDA(20) /*!< IREF current step data 20 */
#define IREF_CUR_STEP_DATA_21 CTL_CSDA(21) /*!< IREF current step data 21 */
#define IREF_CUR_STEP_DATA_22 CTL_CSDA(22) /*!< IREF current step data 22 */
#define IREF_CUR_STEP_DATA_23 CTL_CSDA(23) /*!< IREF current step data 23 */
#define IREF_CUR_STEP_DATA_24 CTL_CSDA(24) /*!< IREF current step data 24 */
#define IREF_CUR_STEP_DATA_25 CTL_CSDA(25) /*!< IREF current step data 25 */
#define IREF_CUR_STEP_DATA_26 CTL_CSDA(26) /*!< IREF current step data 26 */
#define IREF_CUR_STEP_DATA_27 CTL_CSDA(27) /*!< IREF current step data 27 */
#define IREF_CUR_STEP_DATA_28 CTL_CSDA(28) /*!< IREF current step data 28 */
#define IREF_CUR_STEP_DATA_29 CTL_CSDA(29) /*!< IREF current step data 29 */
#define IREF_CUR_STEP_DATA_30 CTL_CSDA(30) /*!< IREF current step data 30 */
#define IREF_CUR_STEP_DATA_31 CTL_CSDA(31) /*!< IREF current step data 31 */
#define IREF_CUR_STEP_DATA_32 CTL_CSDA(32) /*!< IREF current step data 32 */
#define IREF_CUR_STEP_DATA_33 CTL_CSDA(33) /*!< IREF current step data 33 */
#define IREF_CUR_STEP_DATA_34 CTL_CSDA(34) /*!< IREF current step data 34 */
#define IREF_CUR_STEP_DATA_35 CTL_CSDA(35) /*!< IREF current step data 35 */
#define IREF_CUR_STEP_DATA_36 CTL_CSDA(36) /*!< IREF current step data 36 */
#define IREF_CUR_STEP_DATA_37 CTL_CSDA(37) /*!< IREF current step data 37 */
#define IREF_CUR_STEP_DATA_38 CTL_CSDA(38) /*!< IREF current step data 38 */
#define IREF_CUR_STEP_DATA_39 CTL_CSDA(39) /*!< IREF current step data 39 */
#define IREF_CUR_STEP_DATA_40 CTL_CSDA(40) /*!< IREF current step data 40 */
#define IREF_CUR_STEP_DATA_41 CTL_CSDA(41) /*!< IREF current step data 41 */
#define IREF_CUR_STEP_DATA_42 CTL_CSDA(42) /*!< IREF current step data 42 */
#define IREF_CUR_STEP_DATA_43 CTL_CSDA(43) /*!< IREF current step data 43 */
#define IREF_CUR_STEP_DATA_44 CTL_CSDA(44) /*!< IREF current step data 44 */
#define IREF_CUR_STEP_DATA_45 CTL_CSDA(45) /*!< IREF current step data 45 */
#define IREF_CUR_STEP_DATA_46 CTL_CSDA(46) /*!< IREF current step data 46 */
#define IREF_CUR_STEP_DATA_47 CTL_CSDA(47) /*!< IREF current step data 47 */
#define IREF_CUR_STEP_DATA_48 CTL_CSDA(48) /*!< IREF current step data 48 */
#define IREF_CUR_STEP_DATA_49 CTL_CSDA(49) /*!< IREF current step data 49 */
#define IREF_CUR_STEP_DATA_50 CTL_CSDA(50) /*!< IREF current step data 50 */
#define IREF_CUR_STEP_DATA_51 CTL_CSDA(51) /*!< IREF current step data 51 */
#define IREF_CUR_STEP_DATA_52 CTL_CSDA(52) /*!< IREF current step data 52 */
#define IREF_CUR_STEP_DATA_53 CTL_CSDA(53) /*!< IREF current step data 53 */
#define IREF_CUR_STEP_DATA_54 CTL_CSDA(54) /*!< IREF current step data 54 */
#define IREF_CUR_STEP_DATA_55 CTL_CSDA(55) /*!< IREF current step data 54 */
#define IREF_CUR_STEP_DATA_56 CTL_CSDA(56) /*!< IREF current step data 54 */
#define IREF_CUR_STEP_DATA_57 CTL_CSDA(57) /*!< IREF current step data 57 */
#define IREF_CUR_STEP_DATA_58 CTL_CSDA(58) /*!< IREF current step data 58 */
#define IREF_CUR_STEP_DATA_59 CTL_CSDA(59) /*!< IREF current step data 59 */
#define IREF_CUR_STEP_DATA_60 CTL_CSDA(60) /*!< IREF current step data 60 */
#define IREF_CUR_STEP_DATA_61 CTL_CSDA(61) /*!< IREF current step data 61 */
#define IREF_CUR_STEP_DATA_62 CTL_CSDA(62) /*!< IREF current step data 62 */
#define IREF_CUR_STEP_DATA_63 CTL_CSDA(63) /*!< IREF current step data 63 */
/* iref sink current mode*/
#define IREF_SOURCE_CURRENT ((uint32_t)0x00000000) /*!< IREF source current */
#define IREF_SINK_CURRENT BIT(7) /*!< IREF sink current */
/* function declarations */
/* deinit vref */
void ivref_deinit(void);
/* enable vref */
void vref_enable(void);
/* disable vref */
void vref_disable(void);
/* enable vref */
void iref_enable(void);
/* disable iref */
void iref_disable(void);
/* set verf mode */
void vref_mode_set(uint32_t vrefmode);
/* set vrer voltage precision trim value */
void vref_precision_trim_value_set(uint32_t precisiontrim);
/* set iref mode*/
void iref_mode_set(uint32_t irefmode);
/* set iref sink current mode*/
void iref_sink_set(uint32_t irefsinkmode);
/* set iref current precision trim value */
void iref_precision_trim_value_set(uint32_t precisiontrim);
/* set iref step data*/
void iref_step_data_config(uint32_t irefstepdata);
#endif /* GD32F1X0_IVREF_H */
#endif /* GD32F170_190 */

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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_libopt.h Normal file
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/*!
\file gd32f1x0_libopt.h
\brief library optional for gd32f1x0
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_LIBOPT_H
#define GD32F1X0_LIBOPT_H
#include "gd32f1x0_adc.h"
#include "gd32f1x0_cec.h"
#include "gd32f1x0_crc.h"
#include "gd32f1x0_cmp.h"
#include "gd32f1x0_dac.h"
#include "gd32f1x0_dbg.h"
#include "gd32f1x0_dma.h"
#include "gd32f1x0_exti.h"
#include "gd32f1x0_fmc.h"
#include "gd32f1x0_gpio.h"
#include "gd32f1x0_syscfg.h"
#include "gd32f1x0_i2c.h"
#include "gd32f1x0_fwdgt.h"
#include "gd32f1x0_pmu.h"
#include "gd32f1x0_rcu.h"
#include "gd32f1x0_rtc.h"
#include "gd32f1x0_spi.h"
#include "gd32f1x0_timer.h"
#include "gd32f1x0_usart.h"
#include "gd32f1x0_wwdgt.h"
#include "gd32f1x0_misc.h"
#include "gd32f1x0_tsi.h"
#ifdef GD32F170_190
#include "gd32f1x0_slcd.h"
#include "gd32f1x0_opa.h"
#include "gd32f1x0_ivref.h"
#include "gd32f1x0_can.h"
#endif /* GD32F170_190 */
#endif /* GD32F1X0_LIBOPT_H */

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/*!
\file gd32f1x0_misc.h
\brief definitions for the MISC
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_MISC_H
#define GD32F1X0_MISC_H
#include "gd32f1x0.h"
/* constants definitions */
/* set the RAM and FLASH base address */
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000U) /*!< RAM base address */
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000U) /*!< Flash base address */
/* set the NVIC vector table offset mask */
#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80U)
/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000U)
/* priority group - define the pre-emption priority and the subpriority */
#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700U) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600U) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500U) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400U) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300U) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
/* choose the method to enter or exit the lowpower mode */
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02U) /*!< choose the the system whether enter low power mode by exiting from ISR */
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04U) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
#define SCB_SCR_SEVONPEND ((uint8_t)0x10U) /*!< choose the interrupt source that can wake up the lowpower mode */
#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT
#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP
#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND
/* choose the systick clock source */
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
/* function declarations */
/* set the priority group */
void nvic_priority_group_set(uint32_t nvic_prigroup);
/* enable NVIC request */
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
/* disable NVIC request */
void nvic_irq_disable(uint8_t nvic_irq);
/* set the NVIC vector table base address */
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
/* set the state of the low power mode */
void system_lowpower_set(uint8_t lowpower_mode);
/* reset the state of the low power mode */
void system_lowpower_reset(uint8_t lowpower_mode);
/* set the systick clock source */
void systick_clksource_set(uint32_t systick_clksource);
#endif /* GD32F1X0_MISC_H */

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/*!
\file gd32f1x0_opa.h
\brief definitions for the OPA
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifdef GD32F170_190
#ifndef GD32F1X0_OPA_H
#define GD32F1X0_OPA_H
#include "gd32f1x0.h"
/* OPAx(x=0,1,2) definitions */
#define OPA OPA_BASE
#define OPA0 ((uint32_t)0)
#define OPA1 ((uint32_t)1)
#define OPA2 ((uint32_t)2)
/* registers definitions */
#define OPA_CTL REG32(OPA + 0x00U) /*!< OPA control register */
#define OPA_BT REG32(OPA + 0x04U) /*!< OPA bias trimming register for normal mode */
#define OPA_LPBT REG32(OPA + 0x08U) /*!< OPA bias trimming register for low power mode */
/* bits definitions */
/* OPA_CLT */
#define OPA_CTL_OPA0PD BIT(0) /*!< OPA0 power down */
#define OPA_CTL_T3OPA0 BIT(1) /*!< T3 switch enable for OPA0 */
#define OPA_CTL_S1OPA0 BIT(2) /*!< S1 switch enable for OPA0 */
#define OPA_CTL_S2OPA0 BIT(3) /*!< S2 switch enable for OPA0 */
#define OPA_CTL_S3OPA0 BIT(4) /*!< S3 switch enable for OPA0 */
#define OPA_CTL_OPA0CAL_L BIT(5) /*!< OPA1 offset calibration for P diff */
#define OPA_CTL_OPA0CAL_H BIT(6) /*!< OPA1 offset calibration for N diff */
#define OPA_CTL_OPA0LPM BIT(7) /*!< OPA0 low power mode */
#define OPA_CTL_OPA1PD BIT(8) /*!< OPA1 power down */
#define OPA_CTL_T3OPA1 BIT(9) /*!< T3 switch enable for OPA1 */
#define OPA_CTL_S1OPA1 BIT(10) /*!< S1 switch enable for OPA1 */
#define OPA_CTL_S2OPA1 BIT(11) /*!< S2 switch enable for OPA1 */
#define OPA_CTL_S3OPA1 BIT(12) /*!< S3 switch enable for OPA1 */
#define OPA_CTL_OPA1CAL_L BIT(13) /*!< OPA1 offset calibration for P diff */
#define OPA_CTL_OPA1CAL_H BIT(14) /*!< OPA1 offset calibration for N diff */
#define OPA_CTL_OPA1LPM BIT(15) /*!< OPA1 low power mode */
#define OPA_CTL_OPA2PD BIT(16) /*!< OPA2 power down */
#define OPA_CTL_T3OPA2 BIT(17) /*!< T3 switch enable for OPA2 */
#define OPA_CTL_S1OPA2 BIT(18) /*!< S1 switch enable for OPA2 */
#define OPA_CTL_S2OPA2 BIT(19) /*!< S2 switch enable for OPA2 */
#define OPA_CTL_S3OPA2 BIT(20) /*!< S3 switch enable for OPA2 */
#define OPA_CTL_OPA2CAL_L BIT(21) /*!< OPA2 offset calibration for P diff */
#define OPA_CTL_OPA2CAL_H BIT(22) /*!< OPA2 offset calibration for N diff */
#define OPA_CTL_OPA2LPM BIT(23) /*!< OPA2 low power mode */
#define OPA_CTL_S4OPA1 BIT(27) /*!< S4 switch enable for OPA2 */
#define OPA_CTL_OPA_RANGE BIT(28) /*!< Power supply range */
#define OPA_CTL_OPA0CALOUT BIT(29) /*!< OPA0 calibration output */
#define OPA_CTL_OPA1CALOUT BIT(30) /*!< OPA1 calibration output */
#define OPA_CTL_OPA2CALOUT BIT(31) /*!< OPA2 calibration output */
/* OPA_BT */
#define OPA_BT_OA0_TRIM_LOW BITS(0,4) /*!< OPA0, normal mode 5-bit bias trim value for PMOS pairs */
#define OPA_BT_OA0_TRIM_HIGH BITS(5,9) /*!< OPA0, normal mode 5-bit bias trim value for NMOS pairs */
#define OPA_BT_OA1_TRIM_LOW BITS(10,14) /*!< OPA1, normal mode 5-bit bias trim value for PMOS pairs */
#define OPA_BT_OA1_TRIM_HIGH BITS(15,19) /*!< OPA1, normal mode 5-bit bias trim value for NMOS pairs */
#define OPA_BT_OA2_TRIM_LOW BITS(20,24) /*!< OPA2, normal mode 5-bit bias trim value for PMOS pairs*/
#define OPA_BT_OA2_TRIM_HIGH BITS(25,29) /*!< OPA2, normal mode 5-bit bias trim value for NMOS pairs */
#define OPA_BT_OT_USER BIT(31) /*!< OPA trimming mode */
/* OPA_LPBT */
#define OPA_LPBT_OA0_TRIM_LOW BITS(0,4) /*!< OPA0, low-power mode 5-bit bias trim value for PMOS pairs */
#define OPA_LPBT_OA0_TRIM_HIGH BITS(5,9) /*!< OPA0, low-power mode 5-bit bias trim value for NMOS pairs */
#define OPA_LPBT_OA1_TRIM_LOW BITS(10,14) /*!< OPA1, low-power mode 5-bit bias trim value for PMOS pairs */
#define OPA_LPBT_OA1_TRIM_HIGH BITS(15,19) /*!< OPA1, low-power mode 5-bit bias trim value for NMOS pairs */
#define OPA_LPBT_OA2_TRIM_LOW BITS(20,24) /*!< OPA2, low-power mode 5-bit bias trim value for PMOS pairs */
#define OPA_LPBT_OA2_TRIM_HIGH BITS(25,29) /*!< OPA2, low-power mode 5-bit bias trim value for NMOS pairs */
/* constants definitions */
/* opa switch definitions */
#define OPA_T3OPA0 OPA_CTL_T3OPA0 /*!< T3 switch enable for OPA0 */
#define OPA_S1OPA0 OPA_CTL_S1OPA0 /*!< S1 switch enable for OPA0 */
#define OPA_S2OPA0 OPA_CTL_S2OPA0 /*!< S2 switch enable for OPA0 */
#define OPA_S3OPA0 OPA_CTL_S3OPA0 /*!< S3 switch enable for OPA0 */
#define OPA_T3OPA1 OPA_CTL_S3OPA1 /*!< T3 switch enable for OPA1 */
#define OPA_S1OPA1 OPA_CTL_S1OPA1 /*!< S1 switch enable for OPA1 */
#define OPA_S2OPA1 OPA_CTL_S2OPA1 /*!< S2 switch enable for OPA1 */
#define OPA_S3OPA1 OPA_CTL_S3OPA1 /*!< S3 switch enable for OPA1 */
#define OPA_S4OPA1 OPA_CTL_S4OPA1 /*!< S4 switch enable for OPA1 */
#define OPA_T3OPA2 OPA_CTL_T3OPA2 /*!< T3 switch enable for OPA2 */
#define OPA_S1OPA2 OPA_CTL_S1OPA2 /*!< S1 switch enable for OPA2 */
#define OPA_S2OPA2 OPA_CTL_S2OPA2 /*!< S2 switch enable for OPA2 */
#define OPA_S3OPA2 OPA_CTL_S3OPA2 /*!< S3 switch enable for OPA2 */
/* opa trimming mode */
#define OPA_BT_TRIM_FACTORY ((uint32_t)0x00000000) /*!< factory trimming */
#define OPA_BT_TRIM_USER OPA_BT_OT_USER /*!< user trimming */
/* opa input */
#define OPA_INPUT_N ((uint32_t)0x00000040) /*!< NMOS input */
#define OPA_INPUT_P ((uint32_t)0x00000020) /*!< PMOS input */
/* opa power range */
#define OPA_POWRANGE_LOW ((uint32_t)0x00000000) /*!< low power range is selected (VDDA is lower than 3.3V) */
#define OPA_POWRANGE_HIGH OPA_CTL_OPA_RANGE /*!< high power range is selected (VDDA is higher than 3.3V) */
/* function declarations */
/* deinit opa */
void opa_deinit(void);
/* enable opa */
void opa_enable(uint32_t opa_periph);
/* disable opa */
void opa_disable(uint32_t opa_periph);
/* enable opa switch */
void opa_switch_enable(uint32_t opax_swy);
/* disable opa switch */
void opa_switch_disable(uint32_t opax_swy);
/* enable opa low_power mode */
void opa_low_power_enable(uint32_t opa_periph);
/* dis opa low_power mode */
void opa_low_power_disable(uint32_t opa_periph);
/* set opa power range */
void opa_power_range_config(uint32_t powerrange);
/* set opa bias trimming mode */
void opa_trim_mode_set(uint32_t opa_trimmode);
/* set opa bias trimming value normal mode */
void opa_trim_value_config(uint32_t opa_periph,uint32_t opa_input,uint32_t opa_trimvalue);
/* set opa bias trimming value low power mode */
void opa_trim_value_lp_config(uint32_t opa_periph,uint32_t opa_input,uint32_t opa_trimvalue);
/* get opa calibration flag */
FlagStatus opa_cal_out_get(uint32_t opa_periph);
#endif /* GD32F1X0_OPA_H */
#endif /* GD32F170_190 */

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/*!
\file gd32f1x0_pmu.h
\brief definitions for the PMU
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_PMU_H
#define GD32F1X0_PMU_H
#include "gd32f1x0.h"
/* PMU definitions */
#define PMU PMU_BASE
/* registers definitions */
#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */
#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */
/* bits definitions */
/* PMU_CTL */
#define PMU_CTL_LDOLP BIT(0) /*!< ldo low power mode */
#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
/* PMU_CS */
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
#define PMU_CS_STBF BIT(1) /*!< standby flag */
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin 0 enable */
#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin 1 enable */
/* constants definitions */
/* PMU low voltage detector threshold definitions */
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5))
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */
#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */
#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */
#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */
/* PMU flag definitions */
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */
/* PMU ldo definitions */
#define PMU_LDO_NORMAL ((uint32_t)0x00000000) /*!< LDO normal work when pmu enter deepsleep mode */
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when pmu enter deepsleep mode */
/* PMU flag reset definitions */
#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00) /*!< wakeup flag reset */
#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01) /*!< standby flag reset */
/* PMU command constants definitions */
#define WFI_CMD ((uint8_t)0x00) /*!< use WFI command */
#define WFE_CMD ((uint8_t)0x01) /*!< use WFE command */
/* PMU wakeup pin definitions */
#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< wakeup pin 0 */
#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< wakeup pin 1 */
/* function declarations */
/* PMU reset */
void pmu_deinit(void);
/* select low voltage detector threshold */
void pmu_lvd_select(uint32_t lvdt_n);
/* PMU lvd disable */
void pmu_lvd_disable(void);
/* PMU work at sleep mode */
void pmu_to_sleepmode(uint8_t sleepmodecmd);
/* PMU work at deepsleep mode */
void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd);
/* PMU work at standby mode */
void pmu_to_standbymode(uint8_t standbymodecmd);
/* reset flag bit */
void pmu_flag_clear(uint32_t flag_reset);
/* get flag state */
FlagStatus pmu_flag_get(uint32_t flag);
/* PMU backup domain write enable */
void pmu_backup_write_enable(void);
/* PMU backup domain write disable */
void pmu_backup_write_disable(void);
/* wakeup pin enable */
void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
/* wakeup pin disable */
void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
#endif /* GD32F1X0_PMU_H */

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/*!
\file gd32f1x0_rcu.h
\brief definitions for the RCU
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_RCU_H
#define GD32F1X0_RCU_H
#include "gd32f1x0.h"
/* RCU definitions */
#define RCU RCU_BASE
/* registers definitions */
#define RCU_CTL0 REG32(RCU + 0x00U) /*!< control register 0 */
#define RCU_CFG0 REG32(RCU + 0x04U) /*!< configuration register 0 */
#define RCU_INT REG32(RCU + 0x08U) /*!< interrupt register */
#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */
#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */
#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB enable register */
#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */
#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */
#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */
#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source /clock register */
#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */
#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< configuration register 1 */
#define RCU_CFG2 REG32(RCU + 0x30U) /*!< configuration register 2 */
#define RCU_CTL1 REG32(RCU + 0x34U) /*!< control register 1 */
#ifdef GD32F170_190
#define RCU_CFG3 REG32(RCU + 0x80U) /*!< configuration register 3 */
#endif /* GD32F170_190 */
#define RCU_ADDAPB1EN REG32(RCU + 0xF8U) /*!< APB1 additional enable register */
#define RCU_ADDAPB1RST REG32(RCU + 0xFCU) /*!< APB1 additional reset register */
#define RCU_VKEY REG32(RCU + 0x100U) /*!< voltage key register */
#define RCU_DSV REG32(RCU + 0x134U) /*!< deep-sleep mode voltage register */
#ifdef GD32F130_150
#define RCU_PDVSEL REG32(RCU + 0x138U) /*!< power down voltage select register */
#endif /* GD32F130_150 */
/* bits definitions */
/* RCU_CTL0 */
#define RCU_CTL0_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */
#define RCU_CTL0_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */
#define RCU_CTL0_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */
#define RCU_CTL0_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */
#define RCU_CTL0_HXTALEN BIT(16) /*!< external high speed oscillator enable */
#define RCU_CTL0_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */
#define RCU_CTL0_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */
#define RCU_CTL0_CKMEN BIT(19) /*!< HXTAL clock monitor enable */
#define RCU_CTL0_PLLEN BIT(24) /*!< PLL enable */
#define RCU_CTL0_PLLSTB BIT(25) /*!< PLL clock stabilization flag */
/* RCU_CFG0 */
#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */
#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */
#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */
#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */
#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */
#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC clock prescaler selection */
#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */
#define RCU_CFG0_PLLPREDV BIT(17) /*!< HXTAL divider for PLL source clock selection */
#define RCU_CFG0_PLLMF (BIT(27) | BITS(18,21)) /*!< PLL multiply factor */
#ifdef GD32F130_150
#define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */
#define RCU_CFG0_CKOUTSEL BITS(24,26) /*!< CK_OUT clock source selection */
#elif defined (GD32F170_190)
#define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CK_OUT0 clock source selection */
#endif /* GD32F130_150 */
#define RCU_CFG0_PLLMF4 BIT(27) /*!< bit 4 of PLLMF */
#ifdef GD32F130_150
#define RCU_CFG0_CKOUTDIV BITS(28,30) /*!< CK_OUT divider which the CK_OUT frequency can be reduced */
#elif defined (GD32F170_190)
#define RCU_CFG0_CKOUT0DIV BITS(28,30) /*!< CK_OUT0 divider which the CK_OUT0 frequency can be reduced */
#endif /* GD32F130_150 */
#define RCU_CFG0_PLLDV BIT(31) /*!< CK_PLL divide by 1 or 2 for CK_OUT(GD32F130_150) or CK_OUT0(GD32F170_190) */
/* RCU_INT */
#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */
#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */
#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */
#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */
#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */
#ifdef GD32F130_150
#define RCU_INT_IRC14MSTBIF BIT(5) /*!< IRC14M stabilization interrupt flag */
#elif defined (GD32F170_190)
#define RCU_INT_IRC28MSTBIF BIT(5) /*!< IRC28M stabilization interrupt flag */
#endif /* GD32F130_150 */
#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */
#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */
#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */
#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */
#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */
#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */
#ifdef GD32F130_150
#define RCU_INT_IRC14MSTBIE BIT(13) /*!< IRC14M stabilization interrupt enable */
#elif defined (GD32F170_190)
#define RCU_INT_IRC28MSTBIE BIT(13) /*!< IRC28M stabilization interrupt enable */
#endif /* GD32F130_150 */
#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */
#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */
#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */
#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */
#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */
#ifdef GD32F130_150
#define RCU_INT_IRC14MSTBIC BIT(21) /*!< IRC14M stabilization interrupt clear */
#elif defined (GD32F170_190)
#define RCU_INT_IRC28MSTBIC BIT(21) /*!< IRC28M stabilization interrupt clear */
#endif /* GD32F130_150 */
#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */
/* RCU_APB2RST */
#define RCU_APB2RST_CFGRST BIT(0) /*!< system configuration reset */
#define RCU_APB2RST_ADCRST BIT(9) /*!< ADC reset */
#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */
#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */
#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */
#define RCU_APB2RST_TIMER14RST BIT(16) /*!< TIMER14 reset */
#define RCU_APB2RST_TIMER15RST BIT(17) /*!< TIMER15 reset */
#define RCU_APB2RST_TIMER16RST BIT(18) /*!< TIMER16 reset */
/* RCU_APB1RST */
#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 timer reset */
#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 timer reset */
#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 timer reset */
#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 timer reset */
#ifdef GD32F170_190
#define RCU_APB1RST_SLCDRST BIT(9) /*!< SLCD reset */
#endif /* GD32F170_190 */
#define RCU_APB1RST_WWDGTRST BIT(11) /*!< window watchdog timer reset */
#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */
#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */
#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */
#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */
#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */
#ifdef GD32F130_150
#define RCU_APB1RST_USBDRST BIT(23) /*!< USBD reset */
#endif /* GD32F130_150 */
#ifdef GD32F170_190
#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */
#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */
#endif /* GD32F170_190 */
#define RCU_APB1RST_PMURST BIT(28) /*!< power control reset */
#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */
#define RCU_APB1RST_CECRST BIT(30) /*!< HDMI CEC reset */
#ifdef GD32F170_190
#define RCU_APB1RST_OPAIVREFRST BIT(31) /*!< OPA and IVREF reset */
#endif /* GD32F170_190 */
/* RCU_AHBEN */
#define RCU_AHBEN_DMAEN BIT(0) /*!< DMA clock enable */
#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM interface clock enable */
#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable */
#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */
#define RCU_AHBEN_PAEN BIT(17) /*!< GPIO port A clock enable */
#define RCU_AHBEN_PBEN BIT(18) /*!< GPIO port B clock enable */
#define RCU_AHBEN_PCEN BIT(19) /*!< GPIO port C clock enable */
#define RCU_AHBEN_PDEN BIT(20) /*!< GPIO port D clock enable */
#define RCU_AHBEN_PFEN BIT(22) /*!< GPIO port F clock enable */
#define RCU_AHBEN_TSIEN BIT(24) /*!< TSI clock enable */
/* RCU_APB2EN */
#define RCU_APB2EN_CFGCMPEN BIT(0) /*!< system configuration and comparator clock enable */
#define RCU_APB2EN_ADCEN BIT(9) /*!< ADC interface clock enable */
#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 timer clock enable */
#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */
#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */
#define RCU_APB2EN_TIMER14EN BIT(16) /*!< TIMER14 timer clock enable */
#define RCU_APB2EN_TIMER15EN BIT(17) /*!< TIMER15 timer clock enable */
#define RCU_APB2EN_TIMER16EN BIT(18) /*!< TIMER16 timer clock enable */
/* RCU_APB1EN */
#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 timer clock enable */
#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 timer clock enable */
#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 timer clock enable */
#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 timer clock enable */
#ifdef GD32F170_190
#define RCU_APB1EN_SLCDEN BIT(9) /*!< SLCD clock enable */
#endif /* GD32F170_190 */
#define RCU_APB1EN_WWDGTEN BIT(11) /*!< window watchdog timer clock enable */
#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */
#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */
#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */
#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */
#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */
#ifdef GD32F130_150
#define RCU_APB1EN_USBDEN BIT(23) /*!< USBD clock enable */
#endif /* GD32F130_150 */
#ifdef GD32F170_190
#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */
#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */
#endif /* GD32F170_190 */
#define RCU_APB1EN_PMUEN BIT(28) /*!< power interface clock enable */
#define RCU_APB1EN_DACEN BIT(29) /*!< DAC interface clock enable */
#define RCU_APB1EN_CECEN BIT(30) /*!< HDMI CEC interface clock enable */
#ifdef GD32F170_190
#define RCU_APB1EN_OPAIVREFEN BIT(31) /*!< OPA and IVREF clock enable */
#endif /* GD32F170_190 */
/* RCU_BDCTL */
#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */
#define RCU_BDCTL_LXTALSTB BIT(1) /*!< external low-speed oscillator stabilization */
#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */
#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */
#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */
#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */
#define RCU_BDCTL_BKPRST BIT(16) /*!< Backup domain reset */
/* RCU_RSTSCK */
#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */
#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization */
#define RCU_RSTSCK_V12RSTF BIT(23) /*!< V12 domain Power reset flag */
#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */
#define RCU_RSTSCK_OBLRSTF BIT(25) /*!< option byte loader reset flag */
#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */
#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */
#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */
#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */
#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */
#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */
/* RCU_AHBRST */
#define RCU_AHBRST_PARST BIT(17) /*!< GPIO port A reset */
#define RCU_AHBRST_PBRST BIT(18) /*!< GPIO port B reset */
#define RCU_AHBRST_PCRST BIT(19) /*!< GPIO port C reset */
#define RCU_AHBRST_PDRST BIT(20) /*!< GPIO port D reset */
#define RCU_AHBRST_PFRST BIT(22) /*!< GPIO port F reset */
#define RCU_AHBRST_TSIRST BIT(24) /*!< TSI unit reset */
/* RCU_CFG1 */
#define RCU_CFG1_HXTALPREDV BITS(0,3) /*!< CK_HXTAL divider previous PLL */
/* RCU_CFG2 */
#define RCU_CFG2_USART0SEL BITS(0,1) /*!< CK_USART0 clock source selection */
#define RCU_CFG2_CECSEL BIT(6) /*!< CK_CEC clock source selection */
#define RCU_CFG2_ADCSEL BIT(8) /*!< CK_ADC clock source selection */
#ifdef GD32F170_190
#define RCU_CFG2_IRC28MDIV BIT(16) /*!< CK_IRC28M divider 2 or not */
#endif /* GD32F170_190 */
/* RCU_CTL1 */
#ifdef GD32F130_150
#define RCU_CTL1_IRC14MEN BIT(0) /*!< IRC14M internal 14M RC oscillator enable */
#define RCU_CTL1_IRC14MSTB BIT(1) /*!< IRC14M internal 14M RC oscillator stabilization flag */
#define RCU_CTL1_IRC14MADJ BITS(3,7) /*!< internal 14M RC oscillator clock trim adjust value */
#define RCU_CTL1_IRC14MCALIB BITS(8,15) /*!< internal 14M RC oscillator calibration value register */
#elif defined (GD32F170_190)
#define RCU_CTL1_IRC28MEN BIT(0) /*!< IRC28M internal 28M RC oscillator enable */
#define RCU_CTL1_IRC28MSTB BIT(1) /*!< IRC28M internal 28M RC oscillator stabilization flag */
#define RCU_CTL1_IRC28MADJ BITS(3,7) /*!< internal 28M RC oscillator clock trim adjust value */
#define RCU_CTL1_IRC28MCALIB BITS(8,15) /*!< internal 28M RC oscillator calibration value register */
#endif /* GD32F130_150 */
#ifdef GD32F170_190
/* RCU_CFG3 */
#define RCU_CFG3_CKOUT1SRC BITS(0,2) /*!< CKOUT1 clock source selection */
#define RCU_CFG3_CKOUT1DIV BITS(8,13) /*!< CK_OUT1 divider which the CK_OUT1 frequency can be reduced */
#endif /* GD32F170_190 */
/* RCU_ADDAPB1EN */
#define RCU_ADDAPB1EN_I2C2EN BIT(0) /*!< I2C2 unit clock enable */
/* RCU_ADDAPB1RST */
#define RCU_ADDAPB1RST_I2C2RST BIT(0) /*!< I2C2 unit reset */
/* RCU_VKEY */
#define RCU_VKEY_KEY BITS(0,31) /*!< key of RCU_PDVSEL and RCU_DSV register */
/* RCU_DSV */
#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */
#ifdef GD32F130_150
/* RCU_PDVSEL */
#define RCU_PDVSEL_PDRVS BIT(0) /*!< power down voltage select */
#endif /* GD32F130_150 */
/* constants definitions */
/* define the peripheral clock enable bit position and its register index offset */
#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (bitpos))
#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6)))
#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
/* define the voltage key unlock value */
#define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4DU)
/* register index */
enum reg_idx
{
/* peripherals enable */
IDX_AHBEN = 0x14U,
IDX_APB2EN = 0x18U,
IDX_APB1EN = 0x1CU,
IDX_ADDAPB1EN = 0xF8U,
/* peripherals reset */
IDX_AHBRST = 0x28U,
IDX_APB2RST = 0x0CU,
IDX_APB1RST = 0x10U,
IDX_ADDAPB1RST = 0xFCU,
/* clock stabilization */
IDX_CTL0 = 0x00U,
IDX_BDCTL = 0x20U,
IDX_STB = 0x24U,
IDX_CTL1 = 0x34U,
/* peripheral reset */
IDX_RSTSCK = 0x24U,
/* clock stabilization and stuck interrupt */
IDX_INT = 0x08U,
/* configuration register */
IDX_CFG0 = 0x04U,
IDX_CFG2 = 0x30U
};
/* peripheral clock enable */
typedef enum
{
/* AHB peripherals */
RCU_DMA = RCU_REGIDX_BIT(IDX_AHBEN, 0U), /*!< DMA clock */
RCU_CRC = RCU_REGIDX_BIT(IDX_AHBEN, 6U), /*!< CRC clock */
RCU_GPIOA = RCU_REGIDX_BIT(IDX_AHBEN, 17U), /*!< GPIOA clock */
RCU_GPIOB = RCU_REGIDX_BIT(IDX_AHBEN, 18U), /*!< GPIOB clock */
RCU_GPIOC = RCU_REGIDX_BIT(IDX_AHBEN, 19U), /*!< GPIOC clock */
RCU_GPIOD = RCU_REGIDX_BIT(IDX_AHBEN, 20U), /*!< GPIOD clock */
RCU_GPIOF = RCU_REGIDX_BIT(IDX_AHBEN, 22U), /*!< GPIOF clock */
RCU_TSI = RCU_REGIDX_BIT(IDX_AHBEN, 24U), /*!< TSI clock */
/* APB2 peripherals */
RCU_CFGCMP = RCU_REGIDX_BIT(IDX_APB2EN, 0U), /*!< CFGCMP clock */
RCU_ADC = RCU_REGIDX_BIT(IDX_APB2EN, 9U), /*!< ADC clock */
RCU_TIMER0 = RCU_REGIDX_BIT(IDX_APB2EN, 11U), /*!< TIMER0 clock */
RCU_SPI0 = RCU_REGIDX_BIT(IDX_APB2EN, 12U), /*!< SPI0 clock */
RCU_USART0 = RCU_REGIDX_BIT(IDX_APB2EN, 14U), /*!< USART0 clock */
RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U), /*!< TIMER14 clock */
RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U), /*!< TIMER15 clock */
RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U), /*!< TIMER16 clock */
/* APB1 peripherals */
RCU_TIMER1 = RCU_REGIDX_BIT(IDX_APB1EN, 0U), /*!< TIMER1 clock */
RCU_TIMER2 = RCU_REGIDX_BIT(IDX_APB1EN, 1U), /*!< TIMER2 clock */
RCU_TIMER5 = RCU_REGIDX_BIT(IDX_APB1EN, 4U), /*!< TIMER5 clock */
RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U), /*!< TIMER13 clock */
#ifdef GD32F170_190
RCU_SLCD = RCU_REGIDX_BIT(IDX_APB1EN, 9U), /*!< SLCD clock */
#endif /* GD32F170_190 */
RCU_WWDGT = RCU_REGIDX_BIT(IDX_APB1EN, 11U), /*!< WWDGT clock */
RCU_SPI1 = RCU_REGIDX_BIT(IDX_APB1EN, 14U), /*!< SPI1 clock */
RCU_SPI2 = RCU_REGIDX_BIT(IDX_APB1EN, 15U), /*!< SPI2 clock */
RCU_USART1 = RCU_REGIDX_BIT(IDX_APB1EN, 17U), /*!< USART1 clock */
RCU_I2C0 = RCU_REGIDX_BIT(IDX_APB1EN, 21U), /*!< I2C0 clock */
RCU_I2C1 = RCU_REGIDX_BIT(IDX_APB1EN, 22U), /*!< I2C1 clock */
#ifdef GD32F130_150
RCU_USBD = RCU_REGIDX_BIT(IDX_APB1EN, 23U), /*!< USBD clock */
#endif /* GD32F130_150 */
#ifdef GD32F170_190
RCU_CAN0 = RCU_REGIDX_BIT(IDX_APB1EN, 25U), /*!< CAN0 clock */
RCU_CAN1 = RCU_REGIDX_BIT(IDX_APB1EN, 26U), /*!< CAN1 clock */
#endif /* GD32F170_190 */
RCU_PMU = RCU_REGIDX_BIT(IDX_APB1EN, 28U), /*!< PMU clock */
RCU_DAC = RCU_REGIDX_BIT(IDX_APB1EN, 29U), /*!< DAC clock */
RCU_CEC = RCU_REGIDX_BIT(IDX_APB1EN, 30U), /*!< CEC clock */
#ifdef GD32F170_190
RCU_OPAIVREF = RCU_REGIDX_BIT(IDX_APB1EN, 31U), /*!< OPAIVREF clock */
#endif /* GD32F170_190 */
RCU_RTC = RCU_REGIDX_BIT(IDX_BDCTL, 15U), /*!< RTC clock */
/* RCU_ADDAPB1EN */
RCU_I2C2 = RCU_REGIDX_BIT(IDX_ADDAPB1EN, 0U) /*!< I2C2 clock */
}rcu_periph_enum;
/* peripheral clock enable when sleep mode*/
typedef enum
{
/* AHB peripherals */
RCU_SRAM_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 2U), /*!< SRAM clock when sleep mode */
RCU_FMC_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 4U) /*!< FMC clock when sleep mode */
}rcu_periph_sleep_enum;
/* peripherals reset */
typedef enum
{
/* AHB peripherals reset */
RCU_GPIOARST = RCU_REGIDX_BIT(IDX_AHBRST, 17U), /*!< GPIOA reset */
RCU_GPIOBRST = RCU_REGIDX_BIT(IDX_AHBRST, 18U), /*!< GPIOB reset */
RCU_GPIOCRST = RCU_REGIDX_BIT(IDX_AHBRST, 19U), /*!< GPIOC reset */
RCU_GPIODRST = RCU_REGIDX_BIT(IDX_AHBRST, 20U), /*!< GPIOD reset */
RCU_GPIOFRST = RCU_REGIDX_BIT(IDX_AHBRST, 22U), /*!< GPIOF reset */
RCU_TSIRST = RCU_REGIDX_BIT(IDX_AHBRST, 24U), /*!< TSI reset */
/* APB2 peripherals reset */
RCU_CFGCMPRST = RCU_REGIDX_BIT(IDX_APB2RST, 0U), /*!< CFGCMP reset */
RCU_ADCRST = RCU_REGIDX_BIT(IDX_APB2RST, 9U), /*!< ADC reset */
RCU_TIMER0RST = RCU_REGIDX_BIT(IDX_APB2RST, 11U), /*!< TIMER0 reset */
RCU_SPI0RST = RCU_REGIDX_BIT(IDX_APB2RST, 12U), /*!< SPI0 reset */
RCU_USART0RST = RCU_REGIDX_BIT(IDX_APB2RST, 14U), /*!< USART0 reset */
RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U), /*!< TIMER14 reset */
RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U), /*!< TIMER15 reset */
RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U), /*!< TIMER16 reset */
/* APB1 peripherals reset */
RCU_TIMER1RST = RCU_REGIDX_BIT(IDX_APB1RST, 0U), /*!< TIMER1 reset */
RCU_TIMER2RST = RCU_REGIDX_BIT(IDX_APB1RST, 1U), /*!< TIMER2 reset */
RCU_TIMER5RST = RCU_REGIDX_BIT(IDX_APB1RST, 4U), /*!< TIMER5 reset */
RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U), /*!< TIMER13 reset */
#ifdef GD32F170_190
RCU_SLCDRST = RCU_REGIDX_BIT(IDX_APB1RST, 9U), /*!< SLCD reset */
#endif /* GD32F170_190 */
RCU_WWDGTRST = RCU_REGIDX_BIT(IDX_APB1RST, 11U), /*!< WWDGT reset */
RCU_SPI1RST = RCU_REGIDX_BIT(IDX_APB1RST, 14U), /*!< SPI1 reset */
RCU_SPI2RST = RCU_REGIDX_BIT(IDX_APB1RST, 15U), /*!< SPI2 reset */
RCU_USART1RST = RCU_REGIDX_BIT(IDX_APB1RST, 17U), /*!< USART1 reset */
RCU_I2C0RST = RCU_REGIDX_BIT(IDX_APB1RST, 21U), /*!< I2C0 reset */
RCU_I2C1RST = RCU_REGIDX_BIT(IDX_APB1RST, 22U), /*!< I2C1 reset */
#ifdef GD32F130_150
RCU_USBDRST = RCU_REGIDX_BIT(IDX_APB1RST, 23U), /*!< USBD reset */
#endif /* GD32F130_150 */
#ifdef GD32F170_190
RCU_CAN0RST = RCU_REGIDX_BIT(IDX_APB1RST, 25U), /*!< CAN0 reset */
RCU_CAN1RST = RCU_REGIDX_BIT(IDX_APB1RST, 26U), /*!< CAN1 reset */
#endif /* GD32F170_190 */
RCU_PMURST = RCU_REGIDX_BIT(IDX_APB1RST, 28U), /*!< PMU reset */
RCU_DACRST = RCU_REGIDX_BIT(IDX_APB1RST, 29U), /*!< DAC reset */
RCU_CECRST = RCU_REGIDX_BIT(IDX_APB1RST, 30U), /*!< CEC reset */
#ifdef GD32F170_190
RCU_OPAIVREFRST = RCU_REGIDX_BIT(IDX_APB1RST, 31U), /*!< OPAIVREF reset */
#endif /* GD32F170_190 */
/* RCU_ADDAPB1RST */
RCU_I2C2RST = RCU_REGIDX_BIT(IDX_ADDAPB1RST, 0U), /*!< I2C2 reset */
}rcu_periph_reset_enum;
/* clock stabilization and peripheral reset flags */
typedef enum
{
RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_STB, 1U), /*!< IRC40K stabilization flags */
RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_BDCTL, 1U), /*!< LXTAL stabilization flags */
RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_CTL0, 1U), /*!< IRC8M stabilization flags */
RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_CTL0, 17U), /*!< HXTAL stabilization flags */
RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_CTL0, 25U), /*!< PLL stabilization flags */
#ifdef GD32F130_150
RCU_FLAG_IRC14MSTB = RCU_REGIDX_BIT(IDX_CTL1, 1U), /*!< IRC14M stabilization flags */
#elif defined (GD32F170_190)
RCU_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_CTL1, 1U), /*!< IRC28M stabilization flags */
#endif /* GD32F130_150 */
RCU_FLAG_V12RST = RCU_REGIDX_BIT(IDX_RSTSCK, 23U), /*!< V12 reset flags */
RCU_FLAG_OBLRST = RCU_REGIDX_BIT(IDX_RSTSCK, 25U), /*!< OBL reset flags */
RCU_FLAG_EPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 26U), /*!< EPR reset flags */
RCU_FLAG_PORRST = RCU_REGIDX_BIT(IDX_RSTSCK, 27U), /*!< Power reset flags */
RCU_FLAG_SWRST = RCU_REGIDX_BIT(IDX_RSTSCK, 28U), /*!< SW reset flags */
RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 29U), /*!< FWDGT reset flags */
RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 30U), /*!< WWDGT reset flags */
RCU_FLAG_LPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 31U) /*!< LP reset flags */
}rcu_flag_enum;
/* clock stabilization and ckm interrupt flags */
typedef enum
{
RCU_INT_FLAG_IRC40KSTB = RCU_INT_IRC40KSTBIF, /*!< IRC40K stabilization interrupt flag */
RCU_INT_FLAG_LXTALSTB = RCU_INT_LXTALSTBIF, /*!< LXTAL stabilization interrupt flag */
RCU_INT_FLAG_IRC8MSTB = RCU_INT_IRC8MSTBIF, /*!< IRC8M stabilization interrupt flag */
RCU_INT_FLAG_HXTALSTB = RCU_INT_HXTALSTBIF, /*!< HXTAL stabilization interrupt flag */
RCU_INT_FLAG_PLLSTB = RCU_INT_PLLSTBIF, /*!< PLL stabilization interrupt flag */
#ifdef GD32F130_150
RCU_INT_FLAG_IRC14MSTB = RCU_INT_IRC14MSTBIF, /*!< IRC14M stabilization interrupt flag */
#elif defined (GD32F170_190)
RCU_INT_FLAG_IRC28MSTB = RCU_INT_IRC28MSTBIF, /*!< IRC28M stabilization interrupt flag */
#endif /* GD32F130_150 */
RCU_INT_FLAG_CKM = RCU_INT_CKMIF /*!< CKM interrupt flag */
}rcu_int_flag_enum;
/* clock stabilization and stuck interrupt flags clear */
typedef enum
{
RCU_INT_FLAG_IRC40KSTB_CLR = RCU_INT_IRC40KSTBIC, /*!< IRC40K stabilization interrupt flags clear */
RCU_INT_FLAG_LXTALSTB_CLR = RCU_INT_LXTALSTBIC, /*!< LXTAL stabilization interrupt flags clear */
RCU_INT_FLAG_IRC8MSTB_CLR = RCU_INT_IRC8MSTBIC, /*!< IRC8M stabilization interrupt flags clear */
RCU_INT_FLAG_HXTALSTB_CLR = RCU_INT_HXTALSTBIC, /*!< HXTAL stabilization interrupt flags clear */
RCU_INT_FLAG_PLLSTB_CLR = RCU_INT_PLLSTBIC, /*!< PLL stabilization interrupt flags clear */
#ifdef GD32F130_150
RCU_INT_FLAG_IRC14MSTB_CLR = RCU_INT_IRC14MSTBIC, /*!< IRC14M stabilization interrupt flags clear */
#elif defined (GD32F170_190)
RCU_INT_FLAG_IRC28MSTB_CLR = RCU_INT_IRC28MSTBIC, /*!< IRC28M stabilization interrupt flags clear */
#endif /* GD32F130_150 */
RCU_INT_FLAG_CKM_CLR = RCU_INT_CKMIC /*!< CKM interrupt flags clear */
}rcu_int_flag_clear_enum;
/* clock stabilization interrupt enable or disable */
typedef enum
{
RCU_INT_IRC40KSTB = RCU_INT_IRC40KSTBIE, /*!< IRC40K stabilization interrupt */
RCU_INT_LXTALSTB = RCU_INT_LXTALSTBIE, /*!< LXTAL stabilization interrupt */
RCU_INT_IRC8MSTB = RCU_INT_IRC8MSTBIE, /*!< IRC8M stabilization interrupt */
RCU_INT_HXTALSTB = RCU_INT_HXTALSTBIE, /*!< HXTAL stabilization interrupt */
RCU_INT_PLLSTB = RCU_INT_PLLSTBIE, /*!< PLL stabilization interrupt */
#ifdef GD32F130_150
RCU_INT_IRC14MSTB = RCU_INT_IRC14MSTBIE /*!< IRC14M stabilization interrupt */
#elif defined (GD32F170_190)
RCU_INT_IRC28MSTB = RCU_INT_IRC28MSTBIE /*!< IRC28M stabilization interrupt */
#endif /* GD32F130_150 */
}rcu_int_enum;
/* ADC clock source */
typedef enum
{
#ifdef GD32F130_150
RCU_ADCCK_IRC14M = 0, /*!< ADC clock source select IRC14M */
#elif defined (GD32F170_190)
RCU_ADCCK_IRC28M_DIV2 = 0, /*!< ADC clock source select IRC28M/2 */
RCU_ADCCK_IRC28M, /*!< ADC clock source select IRC28M */
#endif /* GD32F130_150 */
RCU_ADCCK_APB2_DIV2, /*!< ADC clock source select APB2/2 */
RCU_ADCCK_APB2_DIV4, /*!< ADC clock source select APB2/4 */
RCU_ADCCK_APB2_DIV6, /*!< ADC clock source select APB2/6 */
RCU_ADCCK_APB2_DIV8 /*!< ADC clock source select APB2/8 */
}rcu_adc_clock_enum;
/* oscillator types */
typedef enum
{
RCU_HXTAL = RCU_REGIDX_BIT(IDX_CTL0, 16U), /*!< HXTAL */
RCU_LXTAL = RCU_REGIDX_BIT(IDX_BDCTL, 0U), /*!< LXTAL */
RCU_IRC8M = RCU_REGIDX_BIT(IDX_CTL0, 0U), /*!< IRC8M */
#ifdef GD32F130_150
RCU_IRC14M = RCU_REGIDX_BIT(IDX_CTL1, 0U), /*!< IRC14M */
#elif defined (GD32F170_190)
RCU_IRC28M = RCU_REGIDX_BIT(IDX_CTL1, 0U), /*!< IRC28M */
#endif /* GD32F130_150 */
RCU_IRC40K = RCU_REGIDX_BIT(IDX_RSTSCK, 0U), /*!< IRC40K */
RCU_PLL_CK = RCU_REGIDX_BIT(IDX_CTL0, 24U) /*!< PLL */
}rcu_osci_type_enum;
/* rcu clock frequency */
typedef enum
{
CK_SYS = 0, /*!< system clock */
CK_AHB, /*!< AHB clock */
CK_APB1, /*!< APB1 clock */
CK_APB2, /*!< APB2 clock */
CK_ADC, /*!< ADC clock */
CK_CEC, /*!< CEC clock */
CK_USART /*!< USART clock */
}rcu_clock_freq_enum;
/* system clock source select */
#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */
#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */
#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */
/* system clock source select status */
#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */
#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */
#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLL */
/* AHB prescaler selection */
#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */
#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */
#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */
#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */
#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */
#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */
#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */
#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */
#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */
/* APB1 prescaler selection */
#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */
#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */
#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */
#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */
#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */
/* APB2 prescaler selection */
#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11))
#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */
#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */
#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */
#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */
#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */
/* ADC clock prescaler selection */
#define CFG0_ADCPSC(regval) (BITS(14,15) & ((uint32_t)(regval) << 14))
#define RCU_ADC_CKAPB2_DIV2 CFG0_ADCPSC(0) /*!< ADC clock prescaler select CK_APB2/2 */
#define RCU_ADC_CKAPB2_DIV4 CFG0_ADCPSC(1) /*!< ADC clock prescaler select CK_APB2/4 */
#define RCU_ADC_CKAPB2_DIV6 CFG0_ADCPSC(2) /*!< ADC clock prescaler select CK_APB2/6 */
#define RCU_ADC_CKAPB2_DIV8 CFG0_ADCPSC(3) /*!< ADC clock prescaler select CK_APB2/8 */
/* PLL clock source selection */
#define RCU_PLLSRC_IRC8M_DIV2 (uint32_t)0x00000000 /*!< PLL clock source select IRC8M/2 */
#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< PLL clock source select HXTAL */
/* HXTAL divider for PLL source clock selection */
#define RCU_PLLPREDV_HXTAL (uint32_t)0x00000000 /*!< HXTAL clock selected */
#define RCU_PLLPREDV_HXTAL_DIV2 RCU_CFG0_PLLPREDV /*!< HXTAL/2 clock selected */
/* PLL multiply factor */
#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18))
#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */
#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */
#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */
#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */
#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */
#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */
#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */
#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */
#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */
#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */
#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */
#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */
#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */
#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */
#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */
#define RCU_PLL_MUL17 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */
#define RCU_PLL_MUL18 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */
#define RCU_PLL_MUL19 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */
#define RCU_PLL_MUL20 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */
#define RCU_PLL_MUL21 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */
#define RCU_PLL_MUL22 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */
#define RCU_PLL_MUL23 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */
#define RCU_PLL_MUL24 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */
#define RCU_PLL_MUL25 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */
#define RCU_PLL_MUL26 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */
#define RCU_PLL_MUL27 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */
#define RCU_PLL_MUL28 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */
#define RCU_PLL_MUL29 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */
#define RCU_PLL_MUL30 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */
#define RCU_PLL_MUL31 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */
#define RCU_PLL_MUL32 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */
#ifdef GD32F130_150
/* USBD clock prescaler selection */
#define CFG0_USBDPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22))
#define RCU_USBD_CKPLL_DIV1_5 CFG0_USBDPSC(0) /*!< USBD clock prescaler select CK_PLL/1.5 */
#define RCU_USBD_CKPLL_DIV1 CFG0_USBDPSC(1) /*!< USBD clock prescaler select CK_PLL */
#define RCU_USBD_CKPLL_DIV2_5 CFG0_USBDPSC(2) /*!< USBD clock prescaler select CK_PLL/2.5 */
#define RCU_USBD_CKPLL_DIV2 CFG0_USBDPSC(3) /*!< USBD clock prescaler select CK_PLL/2 */
/* CK_OUT clock source selection */
#define CFG0_CKOUTSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
#define RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0) /*!< no clock selected */
#define RCU_CKOUTSRC_IRC14M CFG0_CKOUTSEL(1) /*!< CK_OUT clock source select IRC14M */
#define RCU_CKOUTSRC_IRC40K CFG0_CKOUTSEL(2) /*!< CK_OUT clock source select IRC40K */
#define RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3) /*!< CK_OUT clock source select LXTAL */
#define RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4) /*!< CK_OUT clock source select CKSYS */
#define RCU_CKOUTSRC_IRC8M CFG0_CKOUTSEL(5) /*!< CK_OUT clock source select IRC8M */
#define RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6) /*!< CK_OUT clock source select HXTAL */
#define RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7)) /*!< CK_OUT clock source select CK_PLL */
#define RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7) /*!< CK_OUT clock source select CK_PLL/2 */
/* CK_OUT divider */
#define CFG0_CKOUTDIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28))
#define RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0) /*!< CK_OUT is divided by 1 */
#define RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1) /*!< CK_OUT is divided by 2 */
#define RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2) /*!< CK_OUT is divided by 4 */
#define RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3) /*!< CK_OUT is divided by 8 */
#define RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4) /*!< CK_OUT is divided by 16 */
#define RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5) /*!< CK_OUT is divided by 32 */
#define RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6) /*!< CK_OUT is divided by 64 */
#define RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7) /*!< CK_OUT is divided by 128 */
#elif defined (GD32F170_190)
/* CK_OUT0 clock source selection */
#define CFG0_CKOUT0SEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */
#define RCU_CKOUT0SRC_IRC28M CFG0_CKOUT0SEL(1) /*!< CK_OUT0 clock source select IRC28M */
#define RCU_CKOUT0SRC_IRC40K CFG0_CKOUT0SEL(2) /*!< CK_OUT0 clock source select IRC40K */
#define RCU_CKOUT0SRC_LXTAL CFG0_CKOUT0SEL(3) /*!< CK_OUT0 clock source select LXTAL */
#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< CK_OUT0 clock source select CKSYS */
#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< CK_OUT0 clock source select IRC8M */
#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< CK_OUT0 clock source select HXTAL */
#define RCU_CKOUT0SRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUT0SEL(7)) /*!< CK_OUT0 clock source select CK_PLL */
#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_OUT0 clock source select CK_PLL/2 */
/* CK_OUT0 divider */
#define CFG0_CKOUT0DIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28))
#define RCU_CKOUT0_DIV1 CFG0_CKOUT0DIV(0) /*!< CK_OUT0 is divided by 1 */
#define RCU_CKOUT0_DIV2 CFG0_CKOUT0DIV(1) /*!< CK_OUT0 is divided by 2 */
#define RCU_CKOUT0_DIV4 CFG0_CKOUT0DIV(2) /*!< CK_OUT0 is divided by 4 */
#define RCU_CKOUT0_DIV8 CFG0_CKOUT0DIV(3) /*!< CK_OUT0 is divided by 8 */
#define RCU_CKOUT0_DIV16 CFG0_CKOUT0DIV(4) /*!< CK_OUT0 is divided by 16 */
#define RCU_CKOUT0_DIV32 CFG0_CKOUT0DIV(5) /*!< CK_OUT0 is divided by 32 */
#define RCU_CKOUT0_DIV64 CFG0_CKOUT0DIV(6) /*!< CK_OUT0 is divided by 64 */
#define RCU_CKOUT0_DIV128 CFG0_CKOUT0DIV(7) /*!< CK_OUT0 is divided by 128 */
#endif /* GD32F130_150 */
/* CK_PLL divide by 1 or 2 for CK_OUT */
#define RCU_PLLDV_CKPLL_DIV2 (uint32_t)0x00000000U /*!< CK_PLL divide by 2 for CK_OUT */
#define RCU_PLLDV_CKPLL RCU_CFG0_PLLDV /*!< CK_PLL divide by 1 for CK_OUT */
/* LXTAL drive capability */
#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3))
#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */
#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */
#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */
#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */
/* RTC clock entry selection */
#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */
#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< LXTAL selected as RTC source clock */
#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< IRC40K selected as RTC source clock */
#define RCU_RTCSRC_HXTAL_DIV32 BDCTL_RTCSRC(3) /*!< HXTAL/32 selected as RTC source clock */
#ifdef GD32F170_190
/* SLCD clock entry selection */
#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
#define RCU_SLCDSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */
#define RCU_SLCDSRC_LXTAL BDCTL_RTCSRC(1) /*!< LXTAL selected as SLCD source clock */
#define RCU_SLCDSRC_IRC40K BDCTL_RTCSRC(2) /*!< IRC40K selected as SLCD source clock */
#define RCU_SLCDSRC_HXTAL_DIV32 BDCTL_RTCSRC(3) /*!< HXTAL/32 selected as SLCD source clock */
#endif /* GD32F170_190 */
/* CK_HXTAL divider previous PLL */
#define CFG1_HXTALPREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
#define RCU_PLL_HXTAL_DIV1 CFG1_HXTALPREDV(0) /*!< HXTAL input to PLL not divided */
#define RCU_PLL_HXTAL_DIV2 CFG1_HXTALPREDV(1) /*!< HXTAL input to PLL divided by 2 */
#define RCU_PLL_HXTAL_DIV3 CFG1_HXTALPREDV(2) /*!< HXTAL input to PLL divided by 3 */
#define RCU_PLL_HXTAL_DIV4 CFG1_HXTALPREDV(3) /*!< HXTAL input to PLL divided by 4 */
#define RCU_PLL_HXTAL_DIV5 CFG1_HXTALPREDV(4) /*!< HXTAL input to PLL divided by 5 */
#define RCU_PLL_HXTAL_DIV6 CFG1_HXTALPREDV(5) /*!< HXTAL input to PLL divided by 6 */
#define RCU_PLL_HXTAL_DIV7 CFG1_HXTALPREDV(6) /*!< HXTAL input to PLL divided by 7 */
#define RCU_PLL_HXTAL_DIV8 CFG1_HXTALPREDV(7) /*!< HXTAL input to PLL divided by 8 */
#define RCU_PLL_HXTAL_DIV9 CFG1_HXTALPREDV(8) /*!< HXTAL input to PLL divided by 9 */
#define RCU_PLL_HXTAL_DIV10 CFG1_HXTALPREDV(9) /*!< HXTAL input to PLL divided by 10 */
#define RCU_PLL_HXTAL_DIV11 CFG1_HXTALPREDV(10) /*!< HXTAL input to PLL divided by 11 */
#define RCU_PLL_HXTAL_DIV12 CFG1_HXTALPREDV(11) /*!< HXTAL input to PLL divided by 12 */
#define RCU_PLL_HXTAL_DIV13 CFG1_HXTALPREDV(12) /*!< HXTAL input to PLL divided by 13 */
#define RCU_PLL_HXTAL_DIV14 CFG1_HXTALPREDV(13) /*!< HXTAL input to PLL divided by 14 */
#define RCU_PLL_HXTAL_DIV15 CFG1_HXTALPREDV(14) /*!< HXTAL input to PLL divided by 15 */
#define RCU_PLL_HXTAL_DIV16 CFG1_HXTALPREDV(15) /*!< HXTAL input to PLL divided by 16 */
/* USART0 clock source selection */
#define CFG2_USART0SEL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define RCU_USART0SRC_CKAPB2 CFG2_USART0SEL(0) /*!< CK_USART0 select CK_APB2 */
#define RCU_USART0SRC_CKSYS CFG2_USART0SEL(1) /*!< CK_USART0 select CK_SYS */
#define RCU_USART0SRC_LXTAL CFG2_USART0SEL(2) /*!< CK_USART0 select LXTAL */
#define RCU_USART0SRC_IRC8M CFG2_USART0SEL(3) /*!< CK_USART0 select IRC8M */
/* CEC clock source selection */
#define RCU_CECSRC_IRC8M_DIV244 (uint32_t)0x00000000U /*!< CK_CEC clock source select IRC8M/244 */
#define RCU_CECSRC_LXTAL RCU_CFG2_CECSEL /*!< CK_CEC clock source select LXTAL */
#ifdef GD32F130_150
/* ADC clock source selection */
#define RCU_ADCSRC_IRC14M (uint32_t)0x00000000U /*!< ADC clock source select */
#define RCU_ADCSRC_APB2DIV RCU_CFG2_ADCSEL /*!< ADC clock source select */
#elif defined (GD32F170_190)
/* ADC clock source selection */
#define RCU_ADCSRC_IRC28M (uint32_t)0x00000000U /*!< ADC clock source select */
#define RCU_ADCSRC_APB2DIV RCU_CFG2_ADCSEL /*!< ADC clock source select */
/* IRC28M clock divider for ADC */
#define RCU_ADC_IRC28M_DIV2 (uint32_t)0x00000000U /*!< IRC28M/2 select to ADC clock */
#define RCU_ADC_IRC28M_DIV1 RCU_CFG2_IRC28MDIV /*!< IRC28M select to ADC clock */
/* CK_OUT1 clock source selection */
#define CFG3_CKOUT1SRC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
#define RCU_CKOUT1SRC_NONE CFG3_CKOUT1SRC(0) /*!< no clock selected */
#define RCU_CKOUT1SRC_IRC28M CFG3_CKOUT1SRC(1) /*!< CK_OUT1 clock source select IRC28M */
#define RCU_CKOUT1SRC_IRC40K CFG3_CKOUT1SRC(2) /*!< CK_OUT1 clock source select IRC40K */
#define RCU_CKOUT1SRC_LXTAL CFG3_CKOUT1SRC(3) /*!< CK_OUT1 clock source select LXTAL */
#define RCU_CKOUT1SRC_CKSYS CFG3_CKOUT1SRC(4) /*!< CK_OUT1 clock source select CKSYS */
#define RCU_CKOUT1SRC_IRC8M CFG3_CKOUT1SRC(5) /*!< CK_OUT1 clock source select IRC8M */
#define RCU_CKOUT1SRC_HXTAL CFG3_CKOUT1SRC(6) /*!< CK_OUT1 clock source select HXTAL */
#define RCU_CKOUT1SRC_CKPLL_DIV1 0x00000007U /*!< CK_OUT1 clock source select CK_PLL */
#define RCU_CKOUT1SRC_CKPLL_DIV2 0x00000008U /*!< CK_OUT1 clock source select CK_PLL/2 */
/* CK_OUT1 divider */
#define CFG3_CKOUT1DIV(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
#define RCU_CKOUT1_DIV1 CFG3_CKOUT1DIV(0) /*!< CK_OUT1 is divided by 1 */
#define RCU_CKOUT1_DIV2 CFG3_CKOUT1DIV(1) /*!< CK_OUT1 is divided by 2 */
#define RCU_CKOUT1_DIV3 CFG3_CKOUT1DIV(2) /*!< CK_OUT1 is divided by 3 */
#define RCU_CKOUT1_DIV4 CFG3_CKOUT1DIV(3) /*!< CK_OUT1 is divided by 4 */
#define RCU_CKOUT1_DIV5 CFG3_CKOUT1DIV(4) /*!< CK_OUT1 is divided by 5 */
#define RCU_CKOUT1_DIV6 CFG3_CKOUT1DIV(5) /*!< CK_OUT1 is divided by 6 */
#define RCU_CKOUT1_DIV7 CFG3_CKOUT1DIV(6) /*!< CK_OUT1 is divided by 7 */
#define RCU_CKOUT1_DIV8 CFG3_CKOUT1DIV(7) /*!< CK_OUT1 is divided by 8 */
#define RCU_CKOUT1_DIV9 CFG3_CKOUT1DIV(8) /*!< CK_OUT1 is divided by 9 */
#define RCU_CKOUT1_DIV10 CFG3_CKOUT1DIV(9) /*!< CK_OUT1 is divided by 10 */
#define RCU_CKOUT1_DIV11 CFG3_CKOUT1DIV(10) /*!< CK_OUT1 is divided by 11 */
#define RCU_CKOUT1_DIV12 CFG3_CKOUT1DIV(11) /*!< CK_OUT1 is divided by 12 */
#define RCU_CKOUT1_DIV13 CFG3_CKOUT1DIV(12) /*!< CK_OUT1 is divided by 13 */
#define RCU_CKOUT1_DIV14 CFG3_CKOUT1DIV(13) /*!< CK_OUT1 is divided by 14 */
#define RCU_CKOUT1_DIV15 CFG3_CKOUT1DIV(14) /*!< CK_OUT1 is divided by 15 */
#define RCU_CKOUT1_DIV16 CFG3_CKOUT1DIV(15) /*!< CK_OUT1 is divided by 16 */
#define RCU_CKOUT1_DIV17 CFG3_CKOUT1DIV(16) /*!< CK_OUT1 is divided by 17 */
#define RCU_CKOUT1_DIV18 CFG3_CKOUT1DIV(17) /*!< CK_OUT1 is divided by 18 */
#define RCU_CKOUT1_DIV19 CFG3_CKOUT1DIV(18) /*!< CK_OUT1 is divided by 19 */
#define RCU_CKOUT1_DIV20 CFG3_CKOUT1DIV(19) /*!< CK_OUT1 is divided by 20 */
#define RCU_CKOUT1_DIV21 CFG3_CKOUT1DIV(20) /*!< CK_OUT1 is divided by 21 */
#define RCU_CKOUT1_DIV22 CFG3_CKOUT1DIV(21) /*!< CK_OUT1 is divided by 22 */
#define RCU_CKOUT1_DIV23 CFG3_CKOUT1DIV(22) /*!< CK_OUT1 is divided by 23 */
#define RCU_CKOUT1_DIV24 CFG3_CKOUT1DIV(23) /*!< CK_OUT1 is divided by 24 */
#define RCU_CKOUT1_DIV25 CFG3_CKOUT1DIV(24) /*!< CK_OUT1 is divided by 25 */
#define RCU_CKOUT1_DIV26 CFG3_CKOUT1DIV(25) /*!< CK_OUT1 is divided by 26 */
#define RCU_CKOUT1_DIV27 CFG3_CKOUT1DIV(26) /*!< CK_OUT1 is divided by 27 */
#define RCU_CKOUT1_DIV28 CFG3_CKOUT1DIV(27) /*!< CK_OUT1 is divided by 28 */
#define RCU_CKOUT1_DIV29 CFG3_CKOUT1DIV(28) /*!< CK_OUT1 is divided by 29 */
#define RCU_CKOUT1_DIV30 CFG3_CKOUT1DIV(29) /*!< CK_OUT1 is divided by 30 */
#define RCU_CKOUT1_DIV31 CFG3_CKOUT1DIV(30) /*!< CK_OUT1 is divided by 31 */
#define RCU_CKOUT1_DIV32 CFG3_CKOUT1DIV(31) /*!< CK_OUT1 is divided by 32 */
#define RCU_CKOUT1_DIV33 CFG3_CKOUT1DIV(32) /*!< CK_OUT1 is divided by 33 */
#define RCU_CKOUT1_DIV34 CFG3_CKOUT1DIV(33) /*!< CK_OUT1 is divided by 34 */
#define RCU_CKOUT1_DIV35 CFG3_CKOUT1DIV(34) /*!< CK_OUT1 is divided by 35 */
#define RCU_CKOUT1_DIV36 CFG3_CKOUT1DIV(35) /*!< CK_OUT1 is divided by 36 */
#define RCU_CKOUT1_DIV37 CFG3_CKOUT1DIV(36) /*!< CK_OUT1 is divided by 37 */
#define RCU_CKOUT1_DIV38 CFG3_CKOUT1DIV(37) /*!< CK_OUT1 is divided by 38 */
#define RCU_CKOUT1_DIV39 CFG3_CKOUT1DIV(38) /*!< CK_OUT1 is divided by 39 */
#define RCU_CKOUT1_DIV40 CFG3_CKOUT1DIV(39) /*!< CK_OUT1 is divided by 40 */
#define RCU_CKOUT1_DIV41 CFG3_CKOUT1DIV(40) /*!< CK_OUT1 is divided by 41 */
#define RCU_CKOUT1_DIV42 CFG3_CKOUT1DIV(41) /*!< CK_OUT1 is divided by 42 */
#define RCU_CKOUT1_DIV43 CFG3_CKOUT1DIV(42) /*!< CK_OUT1 is divided by 43 */
#define RCU_CKOUT1_DIV44 CFG3_CKOUT1DIV(43) /*!< CK_OUT1 is divided by 44 */
#define RCU_CKOUT1_DIV45 CFG3_CKOUT1DIV(44) /*!< CK_OUT1 is divided by 45 */
#define RCU_CKOUT1_DIV46 CFG3_CKOUT1DIV(45) /*!< CK_OUT1 is divided by 46 */
#define RCU_CKOUT1_DIV47 CFG3_CKOUT1DIV(46) /*!< CK_OUT1 is divided by 47 */
#define RCU_CKOUT1_DIV48 CFG3_CKOUT1DIV(47) /*!< CK_OUT1 is divided by 48 */
#define RCU_CKOUT1_DIV49 CFG3_CKOUT1DIV(48) /*!< CK_OUT1 is divided by 49 */
#define RCU_CKOUT1_DIV50 CFG3_CKOUT1DIV(49) /*!< CK_OUT1 is divided by 50 */
#define RCU_CKOUT1_DIV51 CFG3_CKOUT1DIV(50) /*!< CK_OUT1 is divided by 51 */
#define RCU_CKOUT1_DIV52 CFG3_CKOUT1DIV(51) /*!< CK_OUT1 is divided by 52 */
#define RCU_CKOUT1_DIV53 CFG3_CKOUT1DIV(52) /*!< CK_OUT1 is divided by 53 */
#define RCU_CKOUT1_DIV54 CFG3_CKOUT1DIV(53) /*!< CK_OUT1 is divided by 54 */
#define RCU_CKOUT1_DIV55 CFG3_CKOUT1DIV(54) /*!< CK_OUT1 is divided by 55 */
#define RCU_CKOUT1_DIV56 CFG3_CKOUT1DIV(55) /*!< CK_OUT1 is divided by 56 */
#define RCU_CKOUT1_DIV57 CFG3_CKOUT1DIV(56) /*!< CK_OUT1 is divided by 57 */
#define RCU_CKOUT1_DIV58 CFG3_CKOUT1DIV(57) /*!< CK_OUT1 is divided by 58 */
#define RCU_CKOUT1_DIV59 CFG3_CKOUT1DIV(58) /*!< CK_OUT1 is divided by 59 */
#define RCU_CKOUT1_DIV60 CFG3_CKOUT1DIV(59) /*!< CK_OUT1 is divided by 60 */
#define RCU_CKOUT1_DIV61 CFG3_CKOUT1DIV(60) /*!< CK_OUT1 is divided by 61 */
#define RCU_CKOUT1_DIV62 CFG3_CKOUT1DIV(61) /*!< CK_OUT1 is divided by 62 */
#define RCU_CKOUT1_DIV63 CFG3_CKOUT1DIV(62) /*!< CK_OUT1 is divided by 63 */
#define RCU_CKOUT1_DIV64 CFG3_CKOUT1DIV(63) /*!< CK_OUT1 is divided by 64 */
#endif /* GD32F130_150 */
#ifdef GD32F130_150
/* Deep-sleep mode voltage */
#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */
#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */
#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */
#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */
/*Power down voltage select*/
#define RCU_PDR_V_2_6 (uint32_t)0x00000000U /*!< power down voltage is 2.6V */
#define RCU_PDR_V_1_8 RCU_PDVSEL_PDRVS /*!< power down voltage is 1.8V */
#elif defined (GD32F170_190)
/* Deep-sleep mode voltage */
#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
#define RCU_DEEPSLEEP_V_1_8 DSV_DSLPVS(0) /*!< core voltage is 1.8V in deep-sleep mode */
#define RCU_DEEPSLEEP_V_1_6 DSV_DSLPVS(1) /*!< core voltage is 1.6V in deep-sleep mode */
#define RCU_DEEPSLEEP_V_1_4 DSV_DSLPVS(2) /*!< core voltage is 1.4V in deep-sleep mode */
#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(3) /*!< core voltage is 1.2V in deep-sleep mode */
#endif /* GD32F130_150 */
/* function declarations */
/* deinitialize the RCU */
void rcu_deinit(void);
/* enable the peripherals clock */
void rcu_periph_clock_enable(rcu_periph_enum periph);
/* disable the peripherals clock */
void rcu_periph_clock_disable(rcu_periph_enum periph);
/* enable the peripherals clock when sleep mode */
void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph);
/* disable the peripherals clock when sleep mode */
void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph);
/* reset the peripherals */
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset);
/* disable reset the peripheral */
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset);
/* reset the BKP domain */
void rcu_bkp_reset_enable(void);
/* disable the BKP domain reset */
void rcu_bkp_reset_disable(void);
/* configure the system clock source */
void rcu_system_clock_source_config(uint32_t ck_sys);
/* get the system clock source */
uint32_t rcu_system_clock_source_get(void);
/* configure the AHB prescaler selection */
void rcu_ahb_clock_config(uint32_t ck_ahb);
/* configure the APB1 prescaler selection */
void rcu_apb1_clock_config(uint32_t ck_apb1);
/* configure the APB2 prescaler selection */
void rcu_apb2_clock_config(uint32_t ck_apb2);
/* configure the ADC clock source and prescaler selection */
void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc);
#ifdef GD32F130_150
/* configure the USBD prescaler selection */
void rcu_usbd_clock_config(uint32_t ck_usbd);
/* configure the CK_OUT clock source and divider */
void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div);
#elif defined (GD32F170_190)
/* configure the CK_OUT0 clock source and divider */
void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div);
/* configure the CK_OUT1 clock source and divider */
void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div);
#endif /* GD32F130_150 */
/* configure the PLL clock source selection and PLL multiply factor */
void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul);
/* configure the USART clock source selection */
void rcu_usart_clock_config(uint32_t ck_usart);
/* configure the CEC clock source selection */
void rcu_cec_clock_config(uint32_t ck_cec);
/* configure the RTC clock source selection */
void rcu_rtc_clock_config(uint32_t rtc_clock_source);
#ifdef GD32F170_190
void rcu_slcd_clock_config(uint32_t slcd_clock_source);
#endif /* GD32F170_190 */
/* configure the HXTAL divider used as input of PLL */
void rcu_hxtal_prediv_config(uint32_t hxtal_prediv);
/* configure the LXTAL drive capability */
void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap);
/* get the clock stabilization and periphral reset flags */
FlagStatus rcu_flag_get(rcu_flag_enum flag);
/* clear the reset flag */
void rcu_all_reset_flag_clear(void);
/* get the clock stabilization interrupt and ckm flags */
FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag);
/* clear the interrupt flags */
void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear);
/* enable the stabilization interrupt */
void rcu_interrupt_enable(rcu_int_enum stab_int);
/* disable the stabilization interrupt */
void rcu_interrupt_disable(rcu_int_enum stab_int);
/* wait until oscillator stabilization flags is SET or oscillator startup is timeout */
ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci);
/* turn on the oscillator */
void rcu_osci_on(rcu_osci_type_enum osci);
/* turn off the oscillator */
void rcu_osci_off(rcu_osci_type_enum osci);
/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci);
/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci);
/* enable the HXTAL clock monitor */
void rcu_hxtal_clock_monitor_enable(void);
/* disable the HXTAL clock monitor */
void rcu_hxtal_clock_monitor_disable(void);
/* set the IRC8M adjust value */
void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval);
#ifdef GD32F130_150
/* set the IRC14M adjust value */
void rcu_irc14m_adjust_value_set(uint8_t irc14m_adjval);
#elif defined (GD32F170_190)
/* set the IRC28M adjust value */
void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval);
#endif /* GD32F130_150 */
/* unlock the voltage key */
void rcu_voltage_key_unlock(void);
/* set the deep sleep mode voltage */
void rcu_deepsleep_voltage_set(uint32_t dsvol);
#ifdef GD32F130_150
/* set the power down voltage */
void rcu_power_down_voltage_set(uint32_t pdvol);
#endif /* GD32F130_150 */
/* get the system clock, bus and peripheral clock frequency */
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock);
#endif /* GD32F1X0_RCU_H */

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/*!
\file gd32f1x0_rtc.h
\brief definitions for the RTC
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_RTC_H
#define GD32F1X0_RTC_H
#include "gd32f1x0.h"
/* RTC definitions */
#define RTC RTC_BASE
/* registers definitions */
#define RTC_TIME REG32((RTC) + 0x00U) /*!< RTC time of day register */
#define RTC_DATE REG32((RTC) + 0x04U) /*!< RTC date register */
#define RTC_CTL REG32((RTC) + 0x08U) /*!< RTC control register */
#define RTC_STAT REG32((RTC) + 0x0CU) /*!< RTC status register */
#define RTC_PSC REG32((RTC) + 0x10U) /*!< RTC time prescaler register */
#define RTC_ALRM0TD REG32((RTC) + 0x1CU) /*!< RTC alarm 0 time and date register */
#define RTC_WPK REG32((RTC) + 0x24U) /*!< RTC write protection key register */
#define RTC_SS REG32((RTC) + 0x28U) /*!< RTC sub second register */
#define RTC_SHIFTCTL REG32((RTC) + 0x2CU) /*!< RTC shift function control register */
#define RTC_TTS REG32((RTC) + 0x30U) /*!< RTC time of timestamp register */
#define RTC_DTS REG32((RTC) + 0x34U) /*!< RTC date of timestamp register */
#define RTC_SSTS REG32((RTC) + 0x38U) /*!< RTC sub second of timestamp register */
#define RTC_HRFC REG32((RTC) + 0x3CU) /*!< RTC high resolution frequency compensation registor */
#define RTC_TAMP REG32((RTC) + 0x40U) /*!< RTC tamper register */
#define RTC_ALRM0SS REG32((RTC) + 0x44U) /*!< RTC alarm 0 sub second register */
#define RTC_BKP0 REG32((RTC) + 0x50U) /*!< RTC backup register */
#define RTC_BKP1 REG32((RTC) + 0x54U) /*!< RTC backup register */
#define RTC_BKP2 REG32((RTC) + 0x58U) /*!< RTC backup register */
#define RTC_BKP3 REG32((RTC) + 0x5CU) /*!< RTC backup register */
#define RTC_BKP4 REG32((RTC) + 0x60U) /*!< RTC backup register */
/* bits definitions */
/* RTC_TIME */
#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */
#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */
#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */
#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */
#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */
#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */
#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */
/* RTC_DATE */
#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */
#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */
#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */
#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */
#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */
#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */
#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */
/* RTC_CTL */
#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */
#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */
#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */
#define RTC_CTL_CS BIT(6) /*!< display format of clock system */
#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm function enable */
#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */
#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm interrupt enable */
#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */
#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */
#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */
#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */
#define RTC_CTL_COS BIT(19) /*!< calibration output selection */
#define RTC_CTL_OPOL BIT(20) /*!< output polarity */
#define RTC_CTL_OS BITS(21,22) /*!< output selection */
#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */
/* RTC_STAT */
#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm configuration can be write flag */
#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */
#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */
#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */
#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */
#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */
#define RTC_STAT_ALRM0F BIT(8) /*!< alarm occurs flag */
#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */
#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */
#define RTC_STAT_TP0F BIT(13) /*!< RTC tamp 0 detected flag */
#define RTC_STAT_TP1F BIT(14) /*!< RTC tamp 1 detected flag */
#define RTC_STAT_SCPF BIT(16) /*!< recalibration pending flag */
/* RTC_PSC */
#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */
#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */
/* RTC_ALRM0TD */
#define RTC_ALRM0TD_SCU BITS(0,3) /*!< second units in BCD code */
#define RTC_ALRM0TD_SCT BITS(4,6) /*!< second tens in BCD code */
#define RTC_ALRM0TD_MSKS BIT(7) /*!< alarm second mask bit */
#define RTC_ALRM0TD_MNU BITS(8,11) /*!< minutes units in BCD code */
#define RTC_ALRM0TD_MNT BITS(12,14) /*!< minutes tens in BCD code */
#define RTC_ALRM0TD_MSKM BIT(15) /*!< alarm minutes mask bit */
#define RTC_ALRM0TD_HRU BITS(16,19) /*!< hour units in BCD code */
#define RTC_ALRM0TD_HRT BITS(20,21) /*!< hour units in BCD code */
#define RTC_ALRM0TD_PM BIT(22) /*!< AM/PM flag */
#define RTC_ALRM0TD_MSKH BIT(23) /*!< alarm hour mask bit */
#define RTC_ALRM0TD_DAYU BITS(24,27) /*!< date units or week day in BCD code */
#define RTC_ALRM0TD_DAYT BITS(28,29) /*!< date tens in BCD code */
#define RTC_ALRM0TD_DOWS BIT(30) /*!< day of week selection */
#define RTC_ALRM0TD_MSKD BIT(31) /*!< alarm date mask bit */
/* RTC_WPK */
#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */
/* RTC_SS */
#define RTC_SS_SSC BITS(0,15) /*!< sub second value */
/* RTC_SHIFTCTL */
#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */
#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */
/* RTC_TTS */
#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */
#define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */
#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */
#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */
#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */
#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */
#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */
/* RTC_DTS */
#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */
#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */
#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */
#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */
#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */
/* RTC_SSTS */
#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */
/* RTC_HRFC */
#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */
#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */
#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */
#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */
/* RTC_TAMP */
#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */
#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */
#define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */
#define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */
#define RTC_TAMP_TP1EG BIT(4) /*!< tamper 1 event trigger edge for RTC tamp 1 input */
#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */
#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */
#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */
#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */
#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */
#define RTC_TAMP_PC13VAL BIT(18) /*!< alarm output type control/PC13 output value */
#define RTC_TAMP_PC13MDE BIT(19) /*!< PC13 mode */
#define RTC_TAMP_PC14VAL BIT(20) /*!< PC14 output value */
#define RTC_TAMP_PC14MDE BIT(21) /*!< PC14 mode */
#define RTC_TAMP_PC15VAL BIT(22) /*!< PC15 output value */
#define RTC_TAMP_PC15MDE BIT(23) /*!< PC15 mode */
/* RTC_ALRM0SS */
#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm sub second value */
#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */
/* RTC_BKP0 */
#define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP1 */
#define RTC_BKP1_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP2 */
#define RTC_BKP2_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP3 */
#define RTC_BKP3_DATA BITS(0,31) /*!< backup domain registers */
/* RTC_BKP4 */
#define RTC_BKP4_DATA BITS(0,31) /*!< backup domain registers */
/* constants definitions */
/* structure for initialization of the RTC */
typedef struct
{
uint8_t rtc_year; /*!< RTC year value: 0x0 - 0x99(BCD format) */
uint8_t rtc_month; /*!< RTC month value */
uint8_t rtc_date; /*!< RTC date value: 0x1 - 0x31(BCD format) */
uint8_t rtc_day_of_week; /*!< RTC weekday value */
uint8_t rtc_hour; /*!< RTC hour value */
uint8_t rtc_minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */
uint8_t rtc_second; /*!< RTC second value: 0x0 - 0x59(BCD format) */
uint16_t rtc_factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */
uint16_t rtc_factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */
uint32_t rtc_am_pm; /*!< RTC AM/PM value */
uint32_t rtc_display_format; /*!< RTC time notation */
}rtc_parameter_struct;
/* structure for RTC alarm configuration */
typedef struct
{
uint32_t rtc_alarm_mask; /*!< RTC alarm mask */
uint32_t rtc_weekday_or_date; /*!< specify RTC alarm is on date or weekday */
uint8_t rtc_alarm_day; /*!< RTC alarm date or weekday value*/
uint8_t rtc_alarm_hour; /*!< RTC alarm hour value */
uint8_t rtc_alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */
uint8_t rtc_alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */
uint32_t rtc_am_pm; /*!< RTC alarm AM/PM value */
}rtc_alarm_struct;
/* structure for RTC time-stamp configuration */
typedef struct
{
uint8_t rtc_timestamp_month; /*!< RTC time-stamp month value */
uint8_t rtc_timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */
uint8_t rtc_timestamp_day; /*!< RTC time-stamp weekday value */
uint8_t rtc_timestamp_hour; /*!< RTC time-stamp hour value */
uint8_t rtc_timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */
uint8_t rtc_timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */
uint32_t rtc_am_pm; /*!< RTC time-stamp AM/PM value */
}rtc_timestamp_struct;
/* structure for RTC tamper configuration */
typedef struct
{
uint32_t rtc_tamper_source; /*!< RTC tamper source */
uint32_t rtc_tamper_trigger; /*!< RTC tamper trigger */
uint32_t rtc_tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */
uint32_t rtc_tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */
ControlStatus rtc_tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */
uint32_t rtc_tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */
ControlStatus rtc_tamper_with_timestamp; /*!< RTC tamper time-stamp feature */
}rtc_tamper_struct;
/* time register value */
#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TIME_SC bit field */
#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */
#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TIME_MN bit field */
#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */
#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U))/*!< write value to RTC_TIME_HR bit field */
#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */
#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */
#define RTC_PM RTC_TIME_PM /*!< PM format */
/* date register value */
#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DATE_DAY bit field */
#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */
#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DATE_MON bit field */
#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */
#define RTC_JAN ((uint8_t)0x01U) /*!< Janurary */
#define RTC_FEB ((uint8_t)0x02U) /*!< February */
#define RTC_MAR ((uint8_t)0x03U) /*!< March */
#define RTC_APR ((uint8_t)0x04U) /*!< April */
#define RTC_MAY ((uint8_t)0x05U) /*!< May */
#define RTC_JUN ((uint8_t)0x06U) /*!< June */
#define RTC_JUL ((uint8_t)0x07U) /*!< July */
#define RTC_AUG ((uint8_t)0x08U) /*!< August */
#define RTC_SEP ((uint8_t)0x09U) /*!< September */
#define RTC_OCT ((uint8_t)0x10U) /*!< October */
#define RTC_NOV ((uint8_t)0x11U) /*!< November */
#define RTC_DEC ((uint8_t)0x12U) /*!< December */
#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U))/*!< write value to RTC_DATE_DOW bit field */
#define GET_DATE_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DATE_DOW bit field */
#define RTC_MONDAY ((uint8_t)0x01) /*!< Monday */
#define RTC_TUESDAY ((uint8_t)0x02) /*!< Tuesday */
#define RTC_WEDSDAY ((uint8_t)0x03) /*!< Wednesday */
#define RTC_THURSDAY ((uint8_t)0x04) /*!< Thursday */
#define RTC_FRIDAY ((uint8_t)0x05) /*!< Friday */
#define RTC_SATURDAY ((uint8_t)0x06) /*!< Saturday */
#define RTC_SUNDAY ((uint8_t)0x07) /*!< Sunday */
#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16U))/*!< write value to RTC_DATE_YR bit field */
#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */
/* ctl register value */
#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21U))/*!< write value to RTC_CTL_OS bit field */
#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */
#define RTC_OS_ENABLE CTL_OS(1) /*!< enable alarm flag output */
#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */
#define RTC_CALIBRATION_1HZ RTC_CTL_COEN | RTC_CTL_COS /*!< calibration output of 1Hz is enable */
#define RTC_ALARM_HIGH RTC_CTL_OS_ENABLE /*!< enable alarm flag output with high level */
#define RTC_ALARM_LOW RTC_CTL_OS_ENABLE | RTC_CTL_OPOL /*!< enable alarm flag output with low level*/
#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */
#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */
#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */
#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */
/* psc register value */
#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_PSC_FACTOR_S bit field */
#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */
#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16U))/*!< write value to RTC_PSC_FACTOR_A bit field */
#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */
/* alrm0td register value */
#define ALRM0TD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0TD_SC bit field */
#define GET_ALRM0TD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRM0TD_SC bit field */
#define ALRM0TD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_ALRM0TD_MN bit field */
#define GET_ALRM0TD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRM0TD_MN bit field */
#define ALRM0TD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U))/*!< write value to RTC_ALRM0TD_HR bit field */
#define GET_ALRM0TD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRM0TD_HR bit field */
#define ALRM0TD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24U))/*!< write value to RTC_ALRM0TD_DAY bit field */
#define GET_ALRM0TD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRM0TD_DAY bit field */
#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */
#define RTC_ALARM_DATE_MASK RTC_ALRM0TD_MSKD /*!< alarm date mask */
#define RTC_ALARM_HOUR_MASK RTC_ALRM0TD_MSKH /*!< alarm hour mask */
#define RTC_ALARM_MINUTE_MASK RTC_ALRM0TD_MSKM /*!< alarm minute mask */
#define RTC_ALARM_SECOND_MASK RTC_ALRM0TD_MSKS /*!< alarm second mask */
#define RTC_ALARM_ALL_MASK (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS) /*!< alarm all mask */
#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */
#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRM0TD_DOWS /*!< alarm weekday format selected */
/* wpk register value */
#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_WPK_WPK bit field */
/* ss register value */
#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SS_SSC bit field */
/* shiftctl register value */
#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SHIFTCTL_SFS bit field */
#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */
#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */
/* tts register value */
#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TTS_SC bit field */
#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */
#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TTS_MN bit field */
#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */
#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U))/*!< write value to RTC_TTS_HR bit field */
#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */
/* dts register value */
#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DTS_DAY bit field */
#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */
#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DTS_MON bit field */
#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */
#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U))/*!< write value to RTC_DTS_DOW bit field */
#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */
/* ssts register value */
#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SSTS_SSC bit field */
/* hrfc register value */
#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_HRFC_CMSK bit field */
#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */
#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */
#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */
#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */
#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */
/* tamp register value */
#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TAMP_FREQ bit field */
#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */
#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */
#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */
#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */
#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */
#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */
#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */
#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */
#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11U))/*!< write value to RTC_TAMP_FLT bit field */
#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */
#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */
#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */
#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */
#define TAMP_PRCH(regval) (BITS(13,14 ) & ((uint32_t)(regval) << 13U))/*!< write value to RTC_TAMP_PRCH bit field */
#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */
#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */
#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */
#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */
#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */
#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */
#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */
#define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG /*!< tamper detection is in falling edge mode */
#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */
#define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG /*!< tamper detection is in high level mode */
#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */
#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */
#define RTC_ALARM_OUTPUT_PP RTC_TAMP_PC13VAL /*!< RTC alarm output push-pull mode */
/* alrm0ss register value */
#define ALRM0SS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0SS_SSC bit field */
#define ALRM0SS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U))/*!< write value to RTC_ALRM0SS_MASKSSC bit field */
#define RTC_MASKSSC_0_14 ALRM0SS_MASKSSC(0) /*!< mask alarm subsecond configuration */
#define RTC_MASKSSC_1_14 ALRM0SS_MASKSSC(1) /*!< mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared */
#define RTC_MASKSSC_2_14 ALRM0SS_MASKSSC(2) /*!< mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared */
#define RTC_MASKSSC_3_14 ALRM0SS_MASKSSC(3) /*!< mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared */
#define RTC_MASKSSC_4_14 ALRM0SS_MASKSSC(4) /*!< mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared */
#define RTC_MASKSSC_5_14 ALRM0SS_MASKSSC(5) /*!< mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared */
#define RTC_MASKSSC_6_14 ALRM0SS_MASKSSC(6) /*!< mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared */
#define RTC_MASKSSC_7_14 ALRM0SS_MASKSSC(7) /*!< mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared */
#define RTC_MASKSSC_8_14 ALRM0SS_MASKSSC(8) /*!< mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared */
#define RTC_MASKSSC_9_14 ALRM0SS_MASKSSC(9) /*!< mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared */
#define RTC_MASKSSC_10_14 ALRM0SS_MASKSSC(10) /*!< mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared */
#define RTC_MASKSSC_11_14 ALRM0SS_MASKSSC(11) /*!< mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared */
#define RTC_MASKSSC_12_14 ALRM0SS_MASKSSC(12) /*!< mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared */
#define RTC_MASKSSC_13_14 ALRM0SS_MASKSSC(13) /*!< mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared */
#define RTC_MASKSSC_14 ALRM0SS_MASKSSC(14) /*!< mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared */
#define RTC_MASKSSC_NONE ALRM0SS_MASKSSC(15) /*!< mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared */
/* RTC interrupt source */
#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */
#define RTC_INT_ALARM RTC_CTL_ALRM0IE /*!< RTC alarm interrupt enable */
#define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */
/* write protect key */
#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */
#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */
#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */
/* registers reset value */
#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */
#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */
#define RTC_STAT_RESET ((uint32_t)0x00000007U) /*!< RTC_STAT register reset value */
#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */
/* RTC timeout value */
#define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U) /*!< initialization state flag timeout */
#define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U) /*!< register synchronization flag timeout */
#define RTC_HRFC_TIMEOUT ((uint32_t)0x00001000U) /*!< recalibration pending flag timeout */
#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */
#define RTC_ALRM0WF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */
/* RTC flag */
#define RTC_FLAG_RECALIBRATION RTC_STAT_SCPF /*!< recalibration pending flag */
#define RTC_FLAG_TAMP1 RTC_STAT_TP1F /*!< tamper 1 event flag */
#define RTC_FLAG_TAMP0 RTC_STAT_TP0F /*!< tamper 0 event flag */
#define RTC_FLAG_TIMESTAMP_OVERFLOW RTC_STAT_TSOVRF /*!< time-stamp overflow event flag */
#define RTC_FLAG_TIMESTAMP RTC_STAT_TSF /*!< time-stamp event flag */
#define RTC_FLAG_ALARM0 RTC_STAT_ALRM0F /*!< alarm event flag */
#define RTC_FLAG_INIT RTC_STAT_INITF /*!< init mode event flag */
#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< registers synchronized flag */
#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year parameter configured event flag */
#define RTC_FLAG_SHIFT RTC_STAT_SOPF /*!< shift operation pending flag */
#define RTC_FLAG_ALARM0_WRITTEN RTC_STAT_ALRM0WF /*!< alarm written available flag */
/* function declarations */
/* reset most of the RTC registers */
ErrStatus rtc_deinit(void);
/* initialize RTC registers */
ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct);
/* enter RTC init mode */
ErrStatus rtc_init_mode_enter(void);
/* exit RTC init mode */
void rtc_init_mode_exit(void);
/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */
ErrStatus rtc_register_sync_wait(void);
/* get current time and date */
void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct);
/* get current subsecond value */
uint32_t rtc_subsecond_get(void);
/* configure RTC alarm */
void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time);
/* configure subsecond of RTC alarm */
void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond);
/* get RTC alarm */
void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time);
/* get RTC alarm subsecond */
uint32_t rtc_alarm_subsecond_get(void);
/* enable RTC alarm */
void rtc_alarm_enable(void);
/* disable RTC alarm */
ErrStatus rtc_alarm_disable(void);
/* enable RTC time-stamp */
void rtc_timestamp_enable(uint32_t edge);
/* disable RTC time-stamp */
void rtc_timestamp_disable(void);
/* get RTC timestamp time and date */
void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp);
/* get RTC time-stamp subsecond */
uint32_t rtc_timestamp_subsecond_get(void);
/* enable RTC tamper */
void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper);
/* disable RTC tamper */
void rtc_tamper_disable(uint32_t source);
/* enable specified RTC interrupt */
void rtc_interrupt_enable(uint32_t interrupt);
/* disble specified RTC interrupt */
void rtc_interrupt_disable(uint32_t interrupt);
/* check specified flag */
FlagStatus rtc_flag_get(uint32_t flag);
/* clear specified flag */
void rtc_flag_clear(uint32_t flag);
/* configure RTC alternate output source */
void rtc_alter_output_config(uint32_t source, uint32_t mode);
/* configure RTC calibration register */
ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus);
/* ajust the daylight saving time by adding or substracting one hour from the current time */
void rtc_hour_adjust(uint32_t operation);
/* ajust RTC second or subsecond value of current time */
ErrStatus rtc_second_ajust(uint32_t add, uint32_t minus);
/* enable RTC bypass shadow registers function */
void rtc_bypass_shadow_enable(void);
/* disable RTC bypass shadow registers function */
void rtc_bypass_shadow_disable(void);
/* enable RTC reference clock detection function */
ErrStatus rtc_refclock_detection_enable(void);
/* disable RTC reference clock detection function */
ErrStatus rtc_refclock_detection_disable(void);
#endif /* GD32F1X0_RTC_H */

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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_slcd.h Normal file
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/*!
\file gd32f1x0_slcd.h
\brief definitions for the SLCD
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifdef GD32F170_190
#ifndef GD32F1X0_SLCD_H
#define GD32F1X0_SLCD_H
#include "gd32f1x0.h"
/* SLCD definitions */
#define SLCD SLCD_BASE
/* registers definitions */
#define SLCD_CTL REG32(SLCD + 0x00U) /*!< SLCD controller register */
#define SLCD_CFG REG32(SLCD + 0x04U) /*!< SLCD configuration register */
#define SLCD_STAT REG32(SLCD + 0x08U) /*!< SLCD status flag register */
#define SLCD_STATC REG32(SLCD + 0x0CU) /*!< SLCD status flag clear register */
#define SLCD_DATA0 REG32(SLCD + 0x14U) /*!< SLCD display data register 0 */
#define SLCD_DATA1 REG32(SLCD + 0x1CU) /*!< SLCD display data register 1 */
#define SLCD_DATA2 REG32(SLCD + 0x24U) /*!< SLCD display data register 2 */
#define SLCD_DATA3 REG32(SLCD + 0x2CU) /*!< SLCD display data register 3 */
#define SLCD_DATA4 REG32(SLCD + 0x34U) /*!< SLCD display data register 4 */
#define SLCD_DATA5 REG32(SLCD + 0x3CU) /*!< SLCD display data register 5 */
#define SLCD_DATA6 REG32(SLCD + 0x44U) /*!< SLCD display data register 6 */
#define SLCD_DATA7 REG32(SLCD + 0x4CU) /*!< SLCD display data register 7 */
/* bits definitions */
/* SLCD_CTL */
#define SLCD_CTL_LCDON BIT(0) /*!< SLCD controller start */
#define SLCD_CTL_VSRC BIT(1) /*!< SLCD Voltage source */
#define SLCD_CTL_DUTY BITS(2,4) /*!< duty select */
#define SLCD_CTL_BIAS BITS(5,6) /*!< SLCD bias voltage select */
#define SLCD_CTL_COMS BIT(7) /*!< regular channel start flag */
/* SLCD_CFG */
#define SLCD_CFG_HDEN BIT(0) /*!< high drive enable */
#define SLCD_CFG_SOFIE BIT(1) /*!< start of frame interrupt enable */
#define SLCD_CFG_UPDIE BIT(3) /*!< SLCD update done interrupt enable */
#define SLCD_CFG_PULSE BITS(4,6) /*!< pulse on duration */
#define SLCD_CFG_DTD BITS(7,9) /*!< dead time duration */
#define SLCD_CFG_CONR BITS(10,12) /*!< contrast ratio */
#define SLCD_CFG_BLKDIV BITS(13,15) /*!< blink frequency divider */
#define SLCD_CFG_BLKMOD BITS(16,17) /*!< blink mode */
#define SLCD_CFG_DIV BITS(18,21) /*!< SLCD clock divider */
#define SLCD_CFG_PSC BITS(22,25) /*!< SLCD clock prescaler */
/* SLCD_STAT */
#define SLCD_STAT_ONF BIT(0) /*!< SLCD controller on flag */
#define SLCD_STAT_SOF BIT(1) /*!< start of frame flag */
#define SLCD_STAT_UPRF BIT(2) /*!< SLCD data update request flag */
#define SLCD_STAT_UPDF BIT(3) /*!< update data done flag */
#define SLCD_STAT_VRDYF BIT(4) /*!< SLCD voltage ready flag */
#define SLCD_STAT_SYNF BIT(5) /*!< SLCD register synchronization flag */
/* SLCD_STATC */
#define SLCD_STATC_SOFC BIT(1) /*!< start of frame flag clear */
#define SLCD_STATC_UPDC BIT(3) /*!< SLCD data update done clear bit */
/* SLCD_DATAx */
#define SLCD_DATAx_DATA BITS(0,31) /*!< each bit corresponds to one segment to display */
/* constants definitions */
/* status flag */
#define SLCD_FLAG_ON SLCD_STAT_ONF /*!< SLCD controller on flag */
#define SLCD_FLAG_SOF SLCD_STAT_SOF /*!< start of frame flag */
#define SLCD_FLAG_UPR SLCD_STAT_UPRF /*!< SLCD data update request flag */
#define SLCD_FLAG_UPD SLCD_STAT_UPDF /*!< update data done flag */
#define SLCD_FLAG_VRDY SLCD_STAT_VRDYF /*!< SLCD voltage ready flag */
#define SLCD_FLAG_SYN SLCD_STAT_SYNF /*!< SLCD register synchronization flag */
/* interrupt flag */
#define SLCD_INT_FLAG_SOF ((uint8_t)0x00U) /*!< start of frame interrupt */
#define SLCD_INT_FLAG_UPD ((uint8_t)0x01U) /*!< update data done interrupt */
/* interrupt source */
#define SLCD_INT_SOF ((uint8_t)0x00U) /*!< start of frame interrupt */
#define SLCD_INT_UPD ((uint8_t)0x01U) /*!< update data done interrupt */
/* voltage source definitions */
#define SLCD_VOLTAGE_INTERNAL ((uint8_t)0x00U) /*!< SLCD internal voltage source */
#define SLCD_VOLTAGE_EXTERNAL ((uint8_t)0x01U) /*!< SLCD external voltage source */
/* data register definitions */
#define SLCD_DATA_REG0 ((uint32_t)0x00000000U) /*!< SLCD display data register 0 */
#define SLCD_DATA_REG1 ((uint32_t)0x00000002U) /*!< SLCD display data register 1 */
#define SLCD_DATA_REG2 ((uint32_t)0x00000004U) /*!< SLCD display data register 2 */
#define SLCD_DATA_REG3 ((uint32_t)0x00000006U) /*!< SLCD display data register 3 */
#define SLCD_DATA_REG4 ((uint32_t)0x00000008U) /*!< SLCD display data register 4 */
#define SLCD_DATA_REG5 ((uint32_t)0x0000000AU) /*!< SLCD display data register 5 */
#define SLCD_DATA_REG6 ((uint32_t)0x0000000CU) /*!< SLCD display data register 6 */
#define SLCD_DATA_REG7 ((uint32_t)0x0000000EU) /*!< SLCD display data register 7 */
/* bias voltage definitions */
#define CTL_BIAS(regval) (BITS(5,6) & ((uint32_t)(regval) << 5U))
#define SLCD_BIAS_1_4 CTL_BIAS(0) /*!< 1/4 voltage bias */
#define SLCD_BIAS_1_2 CTL_BIAS(1) /*!< 1/2 voltage bias */
#define SLCD_BIAS_1_3 CTL_BIAS(2) /*!< 1/3 voltage bias */
/* duty select definitions */
#define CTL_DUTY(regval) (BITS(2,4) & ((uint32_t)(regval) << 2U))
#define SLCD_DUTY_STATIC CTL_DUTY(0) /*!< static dutycycle */
#define SLCD_DUTY_1_2 CTL_DUTY(1) /*!< 1/2 dutycycle */
#define SLCD_DUTY_1_3 CTL_DUTY(2) /*!< 1/3 dutycycle */
#define SLCD_DUTY_1_4 CTL_DUTY(3) /*!< 1/4 dutycycle */
#define SLCD_DUTY_1_6 CTL_DUTY(5) /*!< 1/6 dutycycle */
#define SLCD_DUTY_1_8 CTL_DUTY(4) /*!< 1/8 dutycycle */
/* SLCD clock prescaler */
#define CFG_PRE(regval) (BITS(22,25) & ((uint32_t)(regval) << 22U))
#define SLCD_PRESCALER_1 CFG_PRE(0) /*!< PRE = 0 */
#define SLCD_PRESCALER_2 CFG_PRE(1) /*!< PRE = 1 */
#define SLCD_PRESCALER_4 CFG_PRE(2) /*!< PRE = 2 */
#define SLCD_PRESCALER_8 CFG_PRE(3) /*!< PRE = 3 */
#define SLCD_PRESCALER_16 CFG_PRE(4) /*!< PRE = 4 */
#define SLCD_PRESCALER_32 CFG_PRE(5) /*!< PRE = 5 */
#define SLCD_PRESCALER_64 CFG_PRE(6) /*!< PRE = 6 */
#define SLCD_PRESCALER_128 CFG_PRE(7) /*!< PRE = 7 */
#define SLCD_PRESCALER_256 CFG_PRE(8) /*!< PRE = 8 */
#define SLCD_PRESCALER_512 CFG_PRE(9) /*!< PRE = 9 */
#define SLCD_PRESCALER_1024 CFG_PRE(10) /*!< PRE = 10 */
#define SLCD_PRESCALER_2048 CFG_PRE(11) /*!< PRE = 11 */
#define SLCD_PRESCALER_4096 CFG_PRE(12) /*!< PRE = 12 */
#define SLCD_PRESCALER_8192 CFG_PRE(13) /*!< PRE = 13 */
#define SLCD_PRESCALER_16384 CFG_PRE(14) /*!< PRE = 14 */
#define SLCD_PRESCALER_32768 CFG_PRE(15) /*!< PRE = 15 */
/* SLCD clock divider */
#define CFG_DIV(regval) (BITS(18,21) & ((uint32_t)(regval) << 18U))
#define SLCD_DIVIDER_16 CFG_DIV(0) /*!< DIV = 16 */
#define SLCD_DIVIDER_17 CFG_DIV(1) /*!< DIV = 17 */
#define SLCD_DIVIDER_18 CFG_DIV(2) /*!< DIV = 18 */
#define SLCD_DIVIDER_19 CFG_DIV(3) /*!< DIV = 19 */
#define SLCD_DIVIDER_20 CFG_DIV(4) /*!< DIV = 20 */
#define SLCD_DIVIDER_21 CFG_DIV(5) /*!< DIV = 21 */
#define SLCD_DIVIDER_22 CFG_DIV(6) /*!< DIV = 22 */
#define SLCD_DIVIDER_23 CFG_DIV(7) /*!< DIV = 23 */
#define SLCD_DIVIDER_24 CFG_DIV(8) /*!< DIV = 24 */
#define SLCD_DIVIDER_25 CFG_DIV(9) /*!< DIV = 25 */
#define SLCD_DIVIDER_26 CFG_DIV(10) /*!< DIV = 26 */
#define SLCD_DIVIDER_27 CFG_DIV(11) /*!< DIV = 27 */
#define SLCD_DIVIDER_28 CFG_DIV(12) /*!< DIV = 28 */
#define SLCD_DIVIDER_29 CFG_DIV(13) /*!< DIV = 29 */
#define SLCD_DIVIDER_30 CFG_DIV(14) /*!< DIV = 30 */
#define SLCD_DIVIDER_31 CFG_DIV(15) /*!< DIV = 31 */
/* SLCD blink mode */
#define CFG_BLKM(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U))
#define SLCD_BLINKMODE_OFF CFG_BLKM(0) /*!< blink disabled */
#define SLCD_BLINKMODE_SEG0_COM0 CFG_BLKM(1) /*!< blink enabled on SEG[0], COM[0] */
#define SLCD_BLINKMODE_SEG0_ALLCOM CFG_BLKM(2) /*!< blink enabled on SEG[0], all COM */
#define SLCD_BLINKMODE_ALLSEG_ALLCOM CFG_BLKM(3) /*!< blink enabled on all SEG and all COM */
/* SLCD blink frequency divider */
#define CFG_BLKDIV(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U))
#define SLCD_BLINK_FREQUENCY_DIV8 CFG_BLKDIV(0) /*!< blink frequency = fSLCD/8 */
#define SLCD_BLINK_FREQUENCY_DIV16 CFG_BLKDIV(1) /*!< blink frequency = fSLCD/16 */
#define SLCD_BLINK_FREQUENCY_DIV32 CFG_BLKDIV(2) /*!< blink frequency = fSLCD/32 */
#define SLCD_BLINK_FREQUENCY_DIV64 CFG_BLKDIV(3) /*!< blink frequency = fSLCD/64 */
#define SLCD_BLINK_FREQUENCY_DIV128 CFG_BLKDIV(4) /*!< blink frequency = fSLCD/128 */
#define SLCD_BLINK_FREQUENCY_DIV256 CFG_BLKDIV(5) /*!< blink frequency = fSLCD/256 */
#define SLCD_BLINK_FREQUENCY_DIV512 CFG_BLKDIV(6) /*!< blink frequency = fSLCD/512 */
#define SLCD_BLINK_FREQUENCY_DIV1024 CFG_BLKDIV(7) /*!< blink frequency = fSLCD/1024 */
/* SLCD Contrast ratio */
#define CFG_CONR(regval) (BITS(10,12) & ((uint32_t)(regval) << 10U))
#define SLCD_CONTRAST_LEVEL_0 CFG_CONR(0) /*!< maximum SLCD Voltage = 2.60V */
#define SLCD_CONTRAST_LEVEL_1 CFG_CONR(1) /*!< maximum SLCD Voltage = 2.73V */
#define SLCD_CONTRAST_LEVEL_2 CFG_CONR(2) /*!< maximum SLCD Voltage = 2.86V */
#define SLCD_CONTRAST_LEVEL_3 CFG_CONR(3) /*!< maximum SLCD Voltage = 2.99V */
#define SLCD_CONTRAST_LEVEL_4 CFG_CONR(4) /*!< maximum SLCD Voltage = 3.12V */
#define SLCD_CONTRAST_LEVEL_5 CFG_CONR(5) /*!< maximum SLCD Voltage = 3.25V */
#define SLCD_CONTRAST_LEVEL_6 CFG_CONR(6) /*!< maximum SLCD Voltage = 3.38V */
#define SLCD_CONTRAST_LEVEL_7 CFG_CONR(7) /*!< maximum SLCD Voltage = 3.51V */
/* dead time duration */
#define CFG_DD(regval) (BITS(7,9) & ((uint32_t)(regval) << 7U))
#define SLCD_DEADTIME_PERIOD_0 CFG_DD(0) /*!< no dead time */
#define SLCD_DEADTIME_PERIOD_1 CFG_DD(1) /*!< 1 phase inserted between couple of frame */
#define SLCD_DEADTIME_PERIOD_2 CFG_DD(2) /*!< 2 phase inserted between couple of frame */
#define SLCD_DEADTIME_PERIOD_3 CFG_DD(3) /*!< 3 phase inserted between couple of frame */
#define SLCD_DEADTIME_PERIOD_4 CFG_DD(4) /*!< 4 phase inserted between couple of frame */
#define SLCD_DEADTIME_PERIOD_5 CFG_DD(5) /*!< 5 phase inserted between couple of frame */
#define SLCD_DEADTIME_PERIOD_6 CFG_DD(6) /*!< 6 phase inserted between couple of frame */
#define SLCD_DEADTIME_PERIOD_7 CFG_DD(7) /*!< 7 phase inserted between couple of frame */
/* pulse on duration */
#define CFG_PULSE(regval) (BITS(4,6) & ((uint32_t)(regval) << 4U))
#define SLCD_PULSEON_DURATION_0 CFG_PULSE(0) /*!< pulse on duration = 0 */
#define SLCD_PULSEON_DURATION_1 CFG_PULSE(1) /*!< pulse on duration = 1*1/fPRE */
#define SLCD_PULSEON_DURATION_2 CFG_PULSE(2) /*!< pulse on duration = 2*1/fPRE */
#define SLCD_PULSEON_DURATION_3 CFG_PULSE(3) /*!< pulse on duration = 3*1/fPRE */
#define SLCD_PULSEON_DURATION_4 CFG_PULSE(4) /*!< pulse on duration = 4*1/fPRE */
#define SLCD_PULSEON_DURATION_5 CFG_PULSE(5) /*!< pulse on duration = 5*1/fPRE */
#define SLCD_PULSEON_DURATION_6 CFG_PULSE(6) /*!< pulse on duration = 6*1/fPRE */
#define SLCD_PULSEON_DURATION_7 CFG_PULSE(7) /*!< pulse on duration = 7*1/fPRE */
/* function declarations */
/* check the SLCD status flag */
FlagStatus slcd_flag_get(uint8_t slcd_flag);
/* check the SLCD interrupt flag */
FlagStatus slcd_interrupt_flag_get(uint8_t slcd_interrupt);
/* clear the SLCD flag */
void slcd_flag_clear(uint8_t slcd_flag);
/* clear the SLCD interrupt flag */
void slcd_interrupt_flag_clear(uint8_t slcd_interrupt);
/* the SLCD interrupt config */
void slcd_interrupt_config(uint8_t slcd_interrupt,ControlStatus newvalue);
/* SLCD bias voltage select */
void slcd_bias_voltage_select(uint32_t bias_voltage);
/* SLCD duty select */
void slcd_duty_select(uint32_t duty);
/* SLCD input clock config */
void slcd_clock_config(uint32_t prescaler,uint32_t divider);
/* SLCD blink mode config */
void slcd_blink_mode_config(uint32_t mode,uint32_t blink_divider);
/* SLCD contrast ratio config */
void slcd_contrast_ratio_config(uint32_t contrast_ratio);
/* SLCD dead time duration config */
void slcd_dead_time_config(uint32_t dead_time);
/* SLCD pulse on duration config */
void slcd_pulse_on_duration_config(uint32_t duration);
/* SLCD common/segment pad select */
void slcd_com_seg_remap(ControlStatus newvalue);
/* SLCD voltage source select */
void slcd_voltage_source_select(uint8_t voltage_source);
/* SLCD high drive enable */
void slcd_high_drive_config(ControlStatus newvalue);
/* SLCD data register write */
void slcd_data_register_write(uint32_t data_reg,uint32_t data);
/* SLCD data update request */
void slcd_data_update_request(void);
/* SLCD reset */
void slcd_deinit(void);
/* enable SLCD interface */
void slcd_enable(void);
/* disable SLCD interface */
void slcd_disable(void);
#endif /* GD32F1X0_SLCD_H */
#endif /* GD32F170_190 */

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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_spi.h Normal file
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/*!
\file gd32f1x0_spi.h
\brief definitions for the SPI
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_SPI_H
#define GD32F1X0_SPI_H
#include "gd32f1x0.h"
/* SPIx(x=0,1,2) definitions */
#define SPI0 (SPI_BASE + 0x0000F800U)
#define SPI1 SPI_BASE
#define SPI2 (SPI_BASE + 0x00000400U)
/* registers definitions */
#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */
#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/
#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */
#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */
#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */
#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */
#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */
#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */
#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */
#ifdef GD32F170_190
#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad wire control register */
#endif /* GD32F170_190 */
/* bits definitions */
/* SPI_CTL0 */
#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/
#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */
#define SPI_CTL0_MSTMOD BIT(2) /*!< master selection */
#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */
#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/
#define SPI_CTL0_LF BIT(7) /*!< lsb first mode */
#define SPI_CTL0_SWNSS BIT(8) /*!< nss pin selection in nss software mode */
#define SPI_CTL0_SWNSSEN BIT(9) /*!< nss software mode selection */
#define SPI_CTL0_RO BIT(10) /*!< receive only */
#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */
#define SPI_CTL0_CRCNT BIT(12) /*!< CRC transfer next */
#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */
#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/
#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */
/* SPI_CTL1 */
#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */
#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */
#define SPI_CTL1_NSSDRV BIT(2) /*!< drive nss output */
#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */
#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */
#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */
/* SPI_STAT */
#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */
#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */
#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */
#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */
#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */
#define SPI_STAT_CONFERR BIT(5) /*!< SPI config error */
#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error Bit */
#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going Bit*/
/* SPI_DATA */
#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */
/* SPI_CRCPOLY */
#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial register */
/* SPI_RCRC */
#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */
/* SPI_TCRC */
#define SPI_TCRC_TCR BITS(0,15) /*!< RX CRC register */
/* SPI_I2SCTL */
#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */
#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */
#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */
#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */
#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */
#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */
/* SPI_I2S_PSC */
#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */
#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */
#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */
#ifdef GD32F170_190
/* SPI_QCTL */
#define SPI_QCTL_QMOD BIT(0) /*!< quad wire mode enable. */
#define SPI_QCTL_QRD BIT(1) /*!< quad wire read select. */
#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 */
#endif /* GD32F170_190 */
/* constants definitions */
/* SPI and I2S parameter struct definitions */
typedef struct
{
uint32_t device_mode; /*!< SPI master or slave */
uint32_t trans_mode; /*!< SPI transtype */
uint32_t frame_size; /*!< SPI frame size */
uint32_t nss; /*!< SPI NSS control by handware or software */
uint32_t endian; /*!< SPI big endian or little endian */
uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
uint32_t prescale; /*!< SPI prescale factor */
}spi_parameter_struct;
/* SPI mode definitions */
#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */
#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */
/* SPI bidirectional transfer direction */
#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */
#define SPI_BIDIRECTIONAL_RECEIVE ~SPI_CTL0_BDOEN /*!< SPI work in receive-only mode */
/* SPI transmit type */
#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */
#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */
#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */
#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/
/* SPI frame size */
#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */
#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */
/* SPI NSS control mode */
#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */
#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */
/* SPI transmit way */
#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */
#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */
/* SPI clock phase and polarity */
#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */
#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */
#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */
#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */
/* SPI clock prescale factor */
#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */
#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */
#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */
#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */
#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */
#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */
#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */
#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */
/* I2S audio sample rate */
#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */
#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */
#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */
#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */
#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */
#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */
#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */
#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */
#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */
/* I2S frame format */
#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1))
#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */
#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */
#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */
#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */
/* I2S master clock output */
#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */
#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */
/* I2S operation mode */
#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */
#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */
#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */
#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */
/* I2S standard */
#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */
#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */
#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */
#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */
#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
/* I2S clock polarity */
#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
/* SPI DMA constants definitions */
#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
/* SPI CRC constants definitions */
#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */
#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */
/* SPI/I2S interrupt enable/disable constants definitions */
#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */
#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */
#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */
/* SPI/I2S interrupt flag constants definitions */
#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */
#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */
#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt */
#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt */
#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt */
#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt */
/* SPI/I2S flag definitions */
#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */
#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */
#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun flag */
#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< transmit buffer empty interrupt */
#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun flag */
#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
/* function declarations */
/* reset SPI and I2S */
void spi_i2s_deinit(uint32_t spi_periph);
/* initialize SPI parameter */
void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct);
/* enable SPI */
void spi_enable(uint32_t spi_periph);
/* disable SPI */
void spi_disable(uint32_t spi_periph);
/* configure I2S prescaler */
void i2s_psc_config(uint32_t spi_periph,uint32_t audiosample,uint32_t frameformat,uint32_t mckout);
/* initialize I2S parameter */
void i2s_init(uint32_t spi_periph,uint32_t mode,uint32_t standard,uint32_t ckpl);
/* enable I2S */
void i2s_enable(uint32_t spi_periph);
/* disable I2S */
void i2s_disable(uint32_t spi_periph);
/* enable SPI NSS output */
void spi_nss_output_enable(uint32_t spi_periph);
/* disable SPI NSS output */
void spi_nss_output_disable(uint32_t spi_periph);
/* SPI NSS pin high level in software mode */
void spi_nss_internal_high(uint32_t spi_periph);
/* SPI NSS pin low level in software mode */
void spi_nss_internal_low(uint32_t spi_periph);
/* enable SPI DMA */
void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
/* disable SPI DMA */
void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
/* configure SPI/I2S data frame format */
void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
/* SPI transmit data */
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
/* SPI receive data */
uint16_t spi_i2s_data_receive(uint32_t spi_periph);
/* configure SPI bidirectional transfer direction */
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
/* enable SPI and I2S interrupt */
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
/* disable SPI and I2S interrupt */
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
/* get SPI and I2S interrupt status */
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
/* get SPI and I2S flag status */
FlagStatus spi_i2s_flag_get(uint32_t spi_periph,uint32_t flag);
/* clear SPI CRC error flag status */
void spi_crc_error_clear(uint32_t spi_periph);
/* set SPI CRC polynomial */
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
/* get SPI CRC polynomial */
uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
/* turn on SPI CRC function */
void spi_crc_on(uint32_t spi_periph);
/* turn off SPI CRC function */
void spi_crc_off(uint32_t spi_periph);
/* SPI next data is CRC value */
void spi_crc_next(uint32_t spi_periph);
/* get SPI CRC send value or receive value */
uint16_t spi_crc_get(uint32_t spi_periph,uint8_t crc);
#ifdef GD32F170_190
/* enable quad wire SPI */
void qspi_enable(uint32_t spi_periph);
/* disable quad wire SPI */
void qspi_disable(uint32_t spi_periph);
/* enable quad wire SPI write */
void qspi_write_enable(uint32_t spi_periph);
/* enable quad wire SPI read */
void qspi_read_enable(uint32_t spi_periph);
/* enable quad wire SPI_IO2 and SPI_IO3 pin output */
void qspi_io23_output_enable(uint32_t spi_periph);
/* disable quad wire SPI_IO2 and SPI_IO3 pin output */
void qspi_io23_output_disable(uint32_t spi_periph);
#endif /* GD32F170_190 */
#endif /* GD32F1X0_SPI_H */

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/*!
\file gd32f1x0_syscfg.h
\brief definitions for the SYSCFG
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_SYSCFG_H
#define GD32F1X0_SYSCFG_H
#include "gd32f1x0.h"
/* SYSCFG definitions */
#define SYSCFG SYSCFG_BASE
/* registers definitions */
#define SYSCFG_CFG0 REG32(SYSCFG + 0x00U) /*!< system configuration register 0 */
#ifdef GD32F170_190
#define SYSCFG_CFG1 REG32(SYSCFG + 0x04U) /*!< system configuration register 1 */
#endif /* GD32F170_190 */
#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U) /*!< EXTI sources selection register 0 */
#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU) /*!< EXTI sources selection register 1 */
#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U) /*!< EXTI sources selection register 2 */
#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U) /*!< EXTI sources selection register 3 */
#define SYSCFG_CFG2 REG32(SYSCFG + 0x18U) /*!< system configuration register 2 */
/* SYSCFG_CFG0 bits definitions */
#define SYSCFG_CFG0_BOOT_MODE BITS(0,1) /*!< SYSCFG memory remap config */
#define SYSCFG_CFG0_ADC_DMA_RMP BIT(8) /*!< ADC DMA remap config */
#define SYSCFG_CFG0_USART0_TX_DMA_RMP BIT(9) /*!< USART0 Tx DMA remap config */
#define SYSCFG_CFG0_USART0_RX_DMA_RMP BIT(10) /*!< USART0 Rx DMA remap config */
#define SYSCFG_CFG0_TIMER15_DMA_RMP BIT(11) /*!< TIMER 15 DMA remap config */
#define SYSCFG_CFG0_TIMER16_DMA_RMP BIT(12) /*!< TIMER 16 DMA remap config */
#define SYSCFG_CFG0_PB9_HCCE BIT(19) /*!< PB9 pin high current capability enable */
#ifdef GD32F170_190
/* SYSCFG_CFG1 bits definitions */
#define SYSCFG_CFG1_SLCD_DECA BITS(1,3) /*!< decouping capacitance connection for LCD */
#endif /* GD32F170_190 */
/* SYSCFG_EXTISS0 bits definitions */
#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */
#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */
#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */
#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */
/* SYSCFG_EXTISS1 bits definitions */
#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */
#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */
#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */
#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */
/* SYSCFG_EXTISS2 bits definitions */
#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */
#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */
#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */
#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */
/* SYSCFG_EXTISS3 bits definitions */
#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */
#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */
#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */
#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */
/* SYSCFG_CFG2 bits definitions */
#define SYSCFG_CFG2_LOCKUP_LOCK BIT(0) /*!< enable and lock the LOCKUP (Hardfault) output of Cortex-M4 with break input of TIMER0/14/15/16 */
#define SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK BIT(1) /*!< enable and lock the SRAM_PARITY error signal with break input of TIMER0/14/15/16 */
#define SYSCFG_CFG2_LVD_LOCK BIT(2) /*!< enable and lock the LVD connection with TIMER0 break input and also the LVD_EN and LVDSEL[2:0] bits of the power control interface */
#define SYSCFG_CFG2_SRAM_PCEF BIT(8) /*!< SRAM parity check error flag */
/* constants definitions */
/* DMA remap definitions */
#define SYSCFG_DMA_REMAP_ADC SYSCFG_CFG0_ADC_DMA_RMP /*!< ADC DMA remap */
#define SYSCFG_DMA_REMAP_USART0TX SYSCFG_CFG0_USART0_TX_DMA_RMP /*!< USART0_TX DMA remap */
#define SYSCFG_DMA_REMAP_USART0RX SYSCFG_CFG0_USART0_RX_DMA_RMP /*!< USART0_RX DMA remap */
#define SYSCFG_DMA_REMAP_TIMER15 SYSCFG_CFG0_TIMER15_DMA_RMP /*!< TIMER15 DMA remap */
#define SYSCFG_DMA_REMAP_TIMER16 SYSCFG_CFG0_TIMER16_DMA_RMP /*!< TIMER16 DMA remap */
/* high current definitions */
#define SYSCFG_HIGH_CURRENT_ENABLE SYSCFG_CFG0_PB9_HCCE /*!< high current enable */
#define SYSCFG_HIGH_CURRENT_DISABLE (~SYSCFG_CFG0_PB9_HCCE) /*!< high current disable */
/* EXTI source select definition */
#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */
#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */
#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */
#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */
/* EXTI source select mask bits definition */
#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */
/* EXTI source select jumping step definition */
#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */
/* EXTI source select moving step definition */
#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */
/* EXTI source port definitions */
#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */
#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */
#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */
#define EXTI_SOURCE_GPIOD ((uint8_t)0x03U) /*!< EXTI GPIOD configuration */
#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */
/* EXTI source pin definitions */
#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */
#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */
#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */
#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */
#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */
#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */
#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */
#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */
#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */
#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */
#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */
#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */
#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */
#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */
#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */
#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */
/* lock definitions */
#define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK /*!< LOCKUP output lock */
#define SYSCFG_LOCK_SRAM_PARITY_ERROR SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK /*!< SRAM parity error lock */
#define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK /*!< LVD lock */
/* SRAM parity check error flag definitions */
#define SYSCFG_SRAM_PCEF SYSCFG_CFG2_SRAM_PCEF /*!< SRAM parity check error flag */
#ifdef GD32F170_190
#define SYSCFG_LCD_DECA(regval) (BITS(1,3) & ((uint32_t)(regval) << 1))
#define SYSCFG_VLCD_RAIL1 SYSCFG_LCD_DECA(2) /*!< VLCD rail1 */
#define SYSCFG_VLCD_RAIL2 SYSCFG_LCD_DECA(1) /*!< VLCD rail2 */
#define SYSCFG_VLCD_RAIL3 SYSCFG_LCD_DECA(4) /*!< VLCD rail3 */
/* VLCD bias definition */
#define VLCD_BIAS1_2_RAIL1 ((uint8_t)0) /*!< VLCD bias is 1/2, using VLCDrail1 */
#define VLCD_BIAS1_2_RAIL2 ((uint8_t)1) /*!< VLCD bias is 1/2, using VLCDrail2 */
#define VLCD_BIAS1_2_RAIL3 ((uint8_t)2) /*!< VLCD bias is 1/2, using VLCDrail3 */
#define VLCD_BIAS1_3_RAIL1_2 ((uint8_t)3) /*!< VLCD bias is 1/3, using VLCDrail1 and VLCDrail2 */
#define VLCD_BIAS1_3_RAIL1_3 ((uint8_t)4) /*!< VLCD bias is 1/3, using VLCDrail1 and VLCDrail3 */
#define VLCD_BIAS1_4_RAILALL ((uint8_t)5) /*!< VLCD bias is 1/4, using all VLCDrails */
#endif /* GD32F170_190 */
/* function declarations */
/* deinit syscfg module */
void syscfg_deinit(void);
/* enable the DMA channels remapping */
void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap);
/* disable the DMA channels remapping */
void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap);
/* enable PB9 high current capability */
void syscfg_high_current_enable(void);
/* disable PB9 high current capability */
void syscfg_high_current_disable(void);
/* configure the GPIO pin as EXTI Line */
void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin);
/* connect TIMER0/14/15/16 break input to the selected parameter */
void syscfg_lock_config(uint32_t syscfg_lock);
/* check if the specified flag in SYSCFG_CFG2 is set or not */
FlagStatus syscfg_flag_get(uint32_t syscfg_flag);
/* clear the flag in SYSCFG_CFG2 by writing 1 */
void syscfg_flag_clear(uint32_t syscfg_flag);
#ifdef GD32F170_190
/* configure the VLCD intermediate voltage rail */
void syscfg_vlcd_rail_config(uint8_t vlcd_bias);
#endif /* GD32F170_190 */
#endif /* GD32F1X0_SYSCFG_H */

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/*!
\file gd32f1x0_timer.h
\brief definitions for the TIMER
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_TIMER_H
#define GD32F1X0_TIMER_H
#include "gd32f1x0.h"
/* TIMERx(x=0,1,2,5,13,14,15,16) definitions */
#define TIMER0 (TIMER_BASE + 0x00012C00U)
#define TIMER1 (TIMER_BASE + 0x00000000U)
#define TIMER2 (TIMER_BASE + 0x00000400U)
#define TIMER5 (TIMER_BASE + 0x00001000U)
#define TIMER13 (TIMER_BASE + 0x00002000U)
#define TIMER14 (TIMER_BASE + 0x00014000U)
#define TIMER15 (TIMER_BASE + 0x00014400U)
#define TIMER16 (TIMER_BASE + 0x00014800U)
/* registers definitions */
#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */
#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */
#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */
#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */
#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */
#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */
#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */
#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */
#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */
#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */
#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */
#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */
#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */
#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */
#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */
#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */
#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */
#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER complementary channel protection register */
#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */
#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */
#define TIMER_IRMP(timerx) REG32((timerx) + 0x50U) /*!< TIMER channel input remap register(only for TIMER13) */
#define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */
/* bits definitions */
/* TIMER_CTL0 */
#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */
#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */
#define TIMER_CTL0_UPS BIT(2) /*!< update source */
#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */
#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */
#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */
#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */
#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */
/* TIMER_CTL1 */
#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow register enable */
#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */
#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */
#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */
#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */
#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */
#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */
#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */
#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */
#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */
#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */
#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */
/* TIMER_SMCFG */
#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */
#define TIMER_SMCFG_OCRC BIT(3) /*!< OCPRE clear source selection */
#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */
#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */
#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */
#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */
#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */
#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */
/* TIMER_DMAINTEN */
#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */
#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 interrupt enable */
#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 interrupt enable */
#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 interrupt enable */
#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 interrupt enable */
#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation DMA request enable */
#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */
#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */
#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */
#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */
#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */
#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */
#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */
#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< channel control update DMA request enable */
#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */
/* TIMER_INTF */
#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */
#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 interrupt flag */
#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 interrupt flag */
#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 interrupt flag */
#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 interrupt flag */
#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */
#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */
#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */
#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */
#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */
#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */
#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */
/* TIMER_SWEVG */
#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */
#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */
#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */
#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */
#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */
#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */
#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */
#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */
/* TIMER_CHCTL0 */
/* output compare mode */
#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */
#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */
#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */
#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */
#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */
#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */
#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */
#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */
#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */
#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */
/* input capture mode */
#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */
#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */
#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */
#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */
/* TIMER_CHCTL1 */
/* output compare mode */
#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */
#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */
#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */
#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */
#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */
#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */
#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */
#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */
#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */
#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */
/* input capture mode */
#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */
#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */
#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */
#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */
/* TIMER_CHCTL2 */
#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 enable */
#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 polarity */
#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */
#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */
#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 enable */
#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 polarity */
#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */
#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */
#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 enable */
#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 polarity */
#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */
#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */
#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 enable */
#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 polarity */
/* TIMER_CNT */
#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */
/* TIMER_PSC */
#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */
/* TIMER_CAR */
#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */
/* TIMER_CREP */
#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */
/* TIMER_CH0CV */
#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< capture/compare value of channel 0 */
/* TIMER_CH1CV */
#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< capture/compare value of channel 1 */
/* TIMER_CH2CV */
#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< capture/compare value of channel 2 */
/* TIMER_CH3CV */
#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< capture/compare value of channel 3 */
/* TIMER_CCHP */
#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */
#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */
#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */
#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */
#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */
#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */
#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */
#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */
/* TIMER_DMACFG */
#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */
#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */
/* TIMER_DMATB */
#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */
/* TIMER_IRMP */
#define TIMER13_IRMP_CI0_RMP BITS(0,1) /*!< TIMER13 channel 0 input remap */
#ifdef GD32F170_190
/* TIMER_CFG */
#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */
#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */
#endif /* GD32F170_190 */
/* constants definitions */
/* TIMER init parameter struct definitions*/
typedef struct
{
uint16_t prescaler; /*!< prescaler value */
uint16_t alignedmode; /*!< aligned mode */
uint16_t counterdirection; /*!< counter direction */
uint32_t period; /*!< period value */
uint16_t clockdivision; /*!< clock division value */
uint8_t repetitioncounter; /*!< the counter repetition value */
}timer_parameter_struct;
/* break parameter struct definitions*/
typedef struct
{
uint16_t runoffstate; /*!< run mode off-state */
uint16_t ideloffstate; /*!< idle mode off-state */
uint16_t deadtime; /*!< dead time */
uint16_t breakpolarity; /*!< break polarity */
uint16_t outputautostate; /*!< output automatic enable */
uint16_t protectmode; /*!< complementary register protect control */
uint16_t breakstate; /*!< break enable */
}timer_break_parameter_struct;
/* channel output parameter struct definitions */
typedef struct
{
uint16_t outputstate; /*!< channel output state */
uint16_t outputnstate; /*!< channel complementary output state */
uint16_t ocpolarity; /*!< channel output polarity */
uint16_t ocnpolarity; /*!< channel complementary output polarity */
uint16_t ocidlestate; /*!< idle state of channel output */
uint16_t ocnidlestate; /*!< idle state of channel complementary output */
}timer_oc_parameter_struct;
/* channel input parameter struct definitions */
typedef struct
{
uint16_t icpolarity; /*!< channel input polarity */
uint16_t icselection; /*!< channel input mode selection */
uint16_t icprescaler; /*!< channel input capture prescaler */
uint16_t icfilter; /*!< channel input capture filter control */
}timer_ic_parameter_struct;
/* TIMER interrupt enable or disable */
#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */
#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */
#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */
#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */
#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */
#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */
#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */
#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */
/* TIMER flag */
#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */
#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */
#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */
#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */
#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */
#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */
#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */
#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */
#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */
#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */
#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */
#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */
/* TIMER interrupt flag */
#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */
#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */
#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */
#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */
#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */
#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */
#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */
#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF /*!< break interrupt flag */
/* TIMER DMA source enable */
#define TIMER_DMA_UPD ((uint16_t)0x0100U) /*!< update DMA enable */
#define TIMER_DMA_CH0D ((uint16_t)0x0200U) /*!< channel 0 DMA enable */
#define TIMER_DMA_CH1D ((uint16_t)0x0400U) /*!< channel 1 DMA enable */
#define TIMER_DMA_CH2D ((uint16_t)0x0800U) /*!< channel 2 DMA enable */
#define TIMER_DMA_CH3D ((uint16_t)0x1000U) /*!< channel 3 DMA enable */
#define TIMER_DMA_CMTD ((uint16_t)0x2000U) /*!< commutation DMA request enable */
#define TIMER_DMA_TRGD ((uint16_t)0x4000U) /*!< trigger DMA enable */
/* update disable */
#define TIMER_UPDIS_ENABLE TIMER_CTL0_UPDIS /*!< update enable */
#define TIMER_UPDIS_DISABLE ~TIMER_CTL0_UPDIS /*!< update disable */
/* TIMER count enable */
#define TIMER_COUNTER_ENABLE TIMER_CTL0_CEN /*!< count enable */
#define TIMER_COUNTER_DISABLE ~TIMER_CTL0_CEN /*!< count disable */
/* channel DMA request source selection */
#define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U) /*!< DMA request of channel y is sent when update event occurs */
#define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */
/* OCPRE clear source selection */
#define TIMER_OCPRE_CLEAR_SOURCE_ETIF ((uint8_t)0x01U) /*!< OCPRE_CLR_INT is connected to ETIF */
#define TIMER_OCPRE_CLEAR_SOURCE_CLR ((uint8_t)0x00U) /*!< OCPRE_CLR_INT is connected to the OCPRE_CLR input */
/* DMA access base address */
#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U))
#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */
#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */
#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */
#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */
#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */
#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */
#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */
#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */
#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */
#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */
#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */
#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */
#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */
#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */
#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */
#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */
#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */
#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */
#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */
#define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */
/* DMA access burst length */
#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U))
#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */
#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */
#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */
#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */
#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */
#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */
#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */
#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */
#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */
#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */
#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */
#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */
#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */
#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */
#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */
#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */
#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */
#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */
/* TIMER software event generation source */
#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */
#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */
#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */
#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */
#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */
#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */
#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */
#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */
/* center-aligned mode selection */
#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))
#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */
#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */
#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */
#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */
/* TIMER prescaler reload mode */
#define TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U) /*!< the prescaler is loaded right now */
#define TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U) /*!< the prescaler is loaded at the next update event */
/* count direction */
#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */
#define TIMER_COUNTER_DOWN ((uint16_t)0x0010U) /*!< counter down direction */
/* specify division ratio between TIMER clock and dead-time and sampling clock */
#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1, fDTS = fTIMER_CK */
#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2, fDTS = fTIMER_CK/2 */
#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS = fTIMER_CK/4 */
/* single pulse mode */
#define TIMER_SP_MODE_SINGLE ((uint8_t)0x00U) /*!< single pulse mode */
#define TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U) /*!< repetitive pulse mode */
/* auto-reload shadow enable */
#define TIMER_ARSE_ENABLE TIMER_CTL0_ARSE /*!< auto-reload shadow enable */
#define TIMER_ARSE_DISABLE ~TIMER_CTL0_ARSE /*!< auto-reload shadow disable */
/* update source */
#define TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U) /*!< update generate only by counter overflow/underflow */
#define TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */
/* run mode off-state configure */
#define TIMER_ROS_STATE_ENABLE ((uint16_t)0x0800U) /*!< channel OC outputs enable in run mode */
#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< channel OC outputs disable in run mode */
/* idle mode off-state configure */
#define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U) /*!< channel OC outputs enable in idle mode */
#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< channel OC outputs disable in idle mode */
/* break input polarity */
#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */
#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U) /*!< break input polarity is high */
/* output automatic enable */
#define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U) /*!< output automatic enable */
#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */
/* complementary register protect control */
#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */
#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */
#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */
#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */
/* break input enable */
#define TIMER_BREAK_ENABLE ((uint16_t)0x1000U) /*!< break input enable */
#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */
/* TIMER channel y(y=0,1,2,3) */
#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel0(TIMERx(x=0,1,2,13,14,15,16)) */
#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel1(TIMERx(x=0,1,2,14)) */
#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel2(TIMERx(x=0,1,2)) */
#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel3(TIMERx(x=0,1,2)) */
/* channel enable state*/
#define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */
#define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */
/* channel complementary output enable state*/
#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */
#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */
/* channel output polarity */
#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */
#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */
/* channel complementary output polarity */
#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */
#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */
/* idle state of channel output */
#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100U) /*!< idle state of channel output is high */
#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel output is low */
/* idle state of channel complementary output */
#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */
#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */
/* channel output compare mode */
#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */
#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */
#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */
#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */
#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */
#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */
#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */
#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/
/* channel output compare shadow enable */
#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */
#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */
/* channel output compare fast enable */
#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004U) /*!< channel output fast function enable */
#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000U) /*!< channel output fast function disable */
/* channel output compare clear enable. */
#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */
#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */
/* channel control shadow register update control */
#define TIMER_UPDATECTL_CCU ((uint8_t)0x00U) /*!< the shadow registers update by when CMTG bit is set */
#define TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */
/* channel input capture polarity */
#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */
#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */
#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */
/* TIMER input capture selection */
#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */
#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */
#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */
/* channel input capture prescaler */
#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */
#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */
#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4*/
#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */
/* trigger selection */
#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */
#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */
#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */
#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */
#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 edge detector */
#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */
#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */
#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */
/* master mode control */
#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */
#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */
#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */
#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal 0 as trigger output TRGO */
#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */
#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */
#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */
#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */
/* slave mode control */
#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U))
#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */
#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */
#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */
#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */
#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */
#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */
#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */
#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */
/* master slave mode selection */
#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U) /*!< master slave mode enable */
#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U) /*!< master slave mode disable */
/* external trigger prescaler */
#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U))
#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */
#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */
#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */
#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */
/* external trigger polarity */
#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */
#define TIMER_ETP_RISING ~TIMER_SMCFG_ETP /*!< active high or rising edge active */
/* channel 0 trigger input selection */
#define TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U) /*!< TIMER hall sensor mode enable */
#define TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U) /*!< TIMER hall sensor mode disable */
/* channel 0 input remap */
#define IRMP_CI0_RMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U))
#define TIMER_IRMP_CI0_RMP_GPIO IRMP_CI0_RMP(0) /*!< channel 0 input is connected to GPIO */
#define TIMER_IRMP_CI0_RTCCLK IRMP_CI0_RMP(1) /*!< channel 0 input is connected to the RTCCLK */
#define TIMER_IRMP_CI0_HXTALDIV32 IRMP_CI0_RMP(2) /*!< channel 0 input is connected to HXTAL/32 clock */
#define TIMER_IRMP_CI0_CKOUTSEL IRMP_CI0_RMP(3) /*!< channel 0 input is connected to CKOUTSEL */
#ifdef GD32F170_190
/* write CHxVAL register selection */
#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */
#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */
/* the output value selection */
#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */
#define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */
#endif /* GD32F170_190 */
/* function declarations */
/* TIMER timebase*/
/* deinit a timer */
void timer_deinit(uint32_t timer_periph);
/* initialize TIMER counter */
void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara);
/* enable a timer */
void timer_enable(uint32_t timer_periph);
/* disable a timer */
void timer_disable(uint32_t timer_periph);
/* enable the auto reload shadow function */
void timer_auto_reload_shadow_enable(uint32_t timer_periph);
/* disable the auto reload shadow function */
void timer_auto_reload_shadow_disable(uint32_t timer_periph);
/* enable the update event */
void timer_update_event_enable(uint32_t timer_periph);
/* disable the update event */
void timer_update_event_disable(uint32_t timer_periph);
/* set TIMER counter alignment mode */
void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned);
/* set TIMER counter up direction */
void timer_counter_up_direction(uint32_t timer_periph);
/* set TIMER counter down direction */
void timer_counter_down_direction(uint32_t timer_periph);
/* configure TIMER prescaler */
void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload);
/* configure TIMER repetition counter value */
void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition);
/* configure TIMER autoreload register value */
void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload);
/* configure TIMER counter register value */
void timer_counter_value_config(uint32_t timer_periph, uint16_t counter);
/* read TIMER counter value */
uint32_t timer_counter_read(uint32_t timer_periph);
/* read TIMER prescaler value */
uint16_t timer_prescaler_read(uint32_t timer_periph);
/* configure TIMER single pulse mode */
void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode);
/* configure TIMER update source */
void timer_update_source_config(uint32_t timer_periph, uint8_t update);
/* TIMER interrupt and flag*/
/* enable the TIMER interrupt */
void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt);
/* disable the TIMER interrupt */
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt);
/* get TIMER interrupt flag */
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt);
/* clear TIMER interrupt flag */
void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt);
/* get TIMER flag */
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag);
/* clear TIMER flag */
void timer_flag_clear(uint32_t timer_periph, uint32_t flag);
/* TIMER DMA and event*/
/* enable the TIMER DMA */
void timer_dma_enable(uint32_t timer_periph, uint16_t dma);
/* disable the TIMER DMA */
void timer_dma_disable(uint32_t timer_periph, uint16_t dma);
/* channel DMA request source selection */
void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request);
/* configure the TIMER DMA transfer */
void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth);
/* software generate events */
void timer_event_software_generate(uint32_t timer_periph, uint16_t event);
/* TIMER channel complementary protection */
/* configure TIMER break function */
void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara);
/* enable TIMER break function */
void timer_break_enable(uint32_t timer_periph);
/* disable TIMER break function */
void timer_break_disable(uint32_t timer_periph);
/* enable TIMER output automatic function */
void timer_automatic_output_enable(uint32_t timer_periph);
/* disable TIMER output automatic function */
void timer_automatic_output_disable(uint32_t timer_periph);
/* configure TIMER primary output function */
void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue);
/* channel capture/compare control shadow register enable */
void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue);
/* configure TIMER channel control shadow register update control */
void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl);
/* select TIMER OCPRE clear source */
void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear);
/* TIMER channel output */
/* configure TIMER channel output function */
void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara);
/* configure TIMER channel output compare mode */
void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode);
/* configure TIMER channel output pulse value */
void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse);
/* configure TIMER channel output shadow function */
void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow);
/* configure TIMER channel output fast function */
void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast);
/* configure TIMER channel output clear function */
void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear);
/* configure TIMER channel output polarity */
void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity);
/* configure TIMER channel complementary output polarity */
void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity);
/* configure TIMER channel enable state */
void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t state);
/* configure TIMER channel complementary output enable state */
void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate);
/* TIMER channel input */
/* configure TIMER input capture parameter */
void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara);
/* configure TIMER channel input capture prescaler value */
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint32_t prescaler);
/* read TIMER channel capture compare register value */
uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel);
/* configure TIMER input pwm capture function */
void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm);
/* configure TIMER hall sensor mode */
void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode);
/* TIMER master and slave mode */
/* select TIMER input trigger source */
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger);
/* select TIMER master mode output trigger source */
void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger);
/* select TIMER slave mode */
void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode);
/* configure TIMER master slave mode */
void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave);
/* configure TIMER external trigger input */
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter);
/* configure TIMER quadrature decoder mode */
void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity);
/* configure TIMER internal clock mode */
void timer_internal_clock_config(uint32_t timer_periph);
/* configure TIMER the internal trigger as external clock input */
void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger);
/* configure TIMER the external trigger as external clock input */
void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter);
/* configure TIMER the external clock mode 0 */
void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter);
/* configure TIMER the external clock mode 1 */
void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter);
/* disable TIMER the external clock mode 1 */
void timer_external_clock_mode1_disable(uint32_t timer_periph);
/* configure TIMER13 channel0 remap function */
void timer_channel_remap_config(uint32_t timer_periph, uint16_t channel, uint32_t remap);
#ifdef GD32F170_190
/* configure TIMER cc register selection */
void timer_write_cc_register_config(uint32_t timer_periph, uint32_t ccsel);
/* configure TIMER output value selection */
void timer_output_value_selection_config(uint32_t timer_periph, uint32_t outsel);
#endif /* GD32F170_190 */
#endif /* GD32F1X0_TIMER_H */

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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_tsi.h Normal file
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/*!
\file gd32f1x0_tsi.h
\brief definitions for the TSI
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_TSI_H
#define GD32F1X0_TSI_H
#include "gd32f1x0.h"
/* TSI definitions */
#define TSI TSI_BASE /*!< TSI base address */
/* registers definitions */
#define TSI_CTL REG32(TSI + 0x00U) /*!< TSI control register */
#define TSI_INTEN REG32(TSI + 0x04U) /*!< TSI interrupt enable register */
#define TSI_INTC REG32(TSI + 0x08U) /*!< TSI interrupt flag clear register */
#define TSI_INTF REG32(TSI + 0x0CU) /*!< TSI interrupt flag register */
#define TSI_PHM REG32(TSI + 0x10U) /*!< TSI pin hysteresis mode register */
#define TSI_ASW REG32(TSI + 0x18U) /*!< TSI analog switch register */
#define TSI_SAMPCFG REG32(TSI + 0x20U) /*!< TSI sample configuration register */
#define TSI_CHCFG REG32(TSI + 0x28U) /*!< TSI channel configuration register */
#define TSI_GCTL REG32(TSI + 0x30U) /*!< TSI group control register */
#define TSI_G0CYCN REG32(TSI + 0x34U) /*!< TSI group 0 cycle number register */
#define TSI_G1CYCN REG32(TSI + 0x38U) /*!< TSI group 1 cycle number register */
#define TSI_G2CYCN REG32(TSI + 0x3CU) /*!< TSI group 2 cycle number register */
#define TSI_G3CYCN REG32(TSI + 0x40U) /*!< TSI group 3 cycle number register */
#define TSI_G4CYCN REG32(TSI + 0x44U) /*!< TSI group 4 cycle number register */
#define TSI_G5CYCN REG32(TSI + 0x48U) /*!< TSI group 5 cycle number register */
/* bits definitions */
/* TSI_CTL */
#define TSI_CTL_TSIEN BIT(0) /*!< TSI enable */
#define TSI_CTL_TSIS BIT(1) /*!< TSI start */
#define TSI_CTL_TRGMOD BIT(2) /*!< trigger mode selection */
#define TSI_CTL_EGSEL BIT(3) /*!< edge selection */
#define TSI_CTL_PINMOD BIT(4) /*!< pin mode */
#define TSI_CTL_MCN BITS(5,7) /*!< max cycle number of a sequence */
#define TSI_CTL_CTCDIV BITS(12,14) /*!< CTCLK clock division factor */
#define TSI_CTL_ECDIV BIT(15) /*!< ECCLK clock division factor */
#define TSI_CTL_ECEN BIT(16) /*!< extend charge state enable */
#define TSI_CTL_ECDT BITS(17,23) /*!< extend charge State maximum duration time */
#define TSI_CTL_CTDT BITS(24,27) /*!< charge transfer state duration time */
#define TSI_CTL_CDT BITS(28,31) /*!< charge state duration time */
/* TSI_INTEN */
#define TSI_INTEN_CTCFIE BIT(0) /*!< charge transfer complete flag interrupt enable */
#define TSI_INTEN_MNERRIE BIT(1) /*!< max cycle number error interrupt enable */
/* TSI_INTC */
#define TSI_INTC_CCTCF BIT(0) /*!< clear charge transfer complete flag */
#define TSI_INTC_CMNERR BIT(1) /*!< clear max cycle number error */
/* TSI_INTF */
#define TSI_INTF_CTCF BIT(0) /*!< charge transfer complete flag */
#define TSI_INTF_MNERR BIT(1) /*!< max cycle number error */
/* TSI_PHM */
#define TSI_PHM_G0P0 BIT(0) /*!< pin G0P0 Schmitt trigger hysteresis state */
#define TSI_PHM_G0P1 BIT(1) /*!< pin G0P1 Schmitt trigger hysteresis state */
#define TSI_PHM_G0P2 BIT(2) /*!< pin G0P2 Schmitt trigger hysteresis state */
#define TSI_PHM_G0P3 BIT(3) /*!< pin G0P3 Schmitt trigger hysteresis state */
#define TSI_PHM_G1P0 BIT(4) /*!< pin G1P0 Schmitt trigger hysteresis state */
#define TSI_PHM_G1P1 BIT(5) /*!< pin G1P1 Schmitt trigger hysteresis state */
#define TSI_PHM_G1P2 BIT(6) /*!< pin G1P2 Schmitt trigger hysteresis state */
#define TSI_PHM_G1P3 BIT(7) /*!< pin G1P3 Schmitt trigger hysteresis state */
#define TSI_PHM_G2P0 BIT(8) /*!< pin G2P0 Schmitt trigger hysteresis state */
#define TSI_PHM_G2P1 BIT(9) /*!< pin G2P1 Schmitt trigger hysteresis state */
#define TSI_PHM_G2P2 BIT(10) /*!< pin G2P2 Schmitt trigger hysteresis state */
#define TSI_PHM_G2P3 BIT(11) /*!< pin G2P3 Schmitt trigger hysteresis state */
#define TSI_PHM_G3P0 BIT(12) /*!< pin G3P0 Schmitt trigger hysteresis state */
#define TSI_PHM_G3P1 BIT(13) /*!< pin G3P1 Schmitt trigger hysteresis state */
#define TSI_PHM_G3P2 BIT(14) /*!< pin G3P2 Schmitt trigger hysteresis state */
#define TSI_PHM_G3P3 BIT(15) /*!< pin G3P3 Schmitt trigger hysteresis state */
#define TSI_PHM_G4P0 BIT(16) /*!< pin G4P0 Schmitt trigger hysteresis state */
#define TSI_PHM_G4P1 BIT(17) /*!< pin G4P1 Schmitt trigger hysteresis state */
#define TSI_PHM_G4P2 BIT(18) /*!< pin G4P2 Schmitt trigger hysteresis state */
#define TSI_PHM_G4P3 BIT(19) /*!< pin G4P3 Schmitt trigger hysteresis state */
#define TSI_PHM_G5P0 BIT(20) /*!< pin G5P0 Schmitt trigger hysteresis state */
#define TSI_PHM_G5P1 BIT(21) /*!< pin G5P1 Schmitt trigger hysteresis state */
#define TSI_PHM_G5P2 BIT(22) /*!< pin G5P2 Schmitt trigger hysteresis state */
#define TSI_PHM_G5P3 BIT(23) /*!< pin G5P3 Schmitt trigger hysteresis state */
/* TSI_ASW */
#define TSI_ASW_G0P0 BIT(0) /*!< pin G0P0 analog switch state */
#define TSI_ASW_G0P1 BIT(1) /*!< pin G0P2 analog switch state */
#define TSI_ASW_G0P2 BIT(2) /*!< pin G0P3 analog switch state */
#define TSI_ASW_G0P3 BIT(3) /*!< pin G0P4 analog switch state */
#define TSI_ASW_G1P0 BIT(4) /*!< pin G1P0 analog switch state */
#define TSI_ASW_G1P1 BIT(5) /*!< pin G1P1 analog switch state */
#define TSI_ASW_G1P2 BIT(6) /*!< pin G1P2 analog switch state */
#define TSI_ASW_G1P3 BIT(7) /*!< pin G1P3 analog switch state */
#define TSI_ASW_G2P0 BIT(8) /*!< pin G2P0 analog switch state */
#define TSI_ASW_G2P1 BIT(9) /*!< pin G2P1 analog switch state */
#define TSI_ASW_G2P2 BIT(10) /*!< pin G2P2 analog switch state */
#define TSI_ASW_G2P3 BIT(11) /*!< pin G2P3 analog switch state */
#define TSI_ASW_G3P0 BIT(12) /*!< pin G3P0 analog switch state */
#define TSI_ASW_G3P1 BIT(13) /*!< pin G3P1 analog switch state */
#define TSI_ASW_G3P2 BIT(14) /*!< pin G3P2 analog switch state */
#define TSI_ASW_G3P3 BIT(15) /*!< pin G3P3 analog switch state */
#define TSI_ASW_G4P0 BIT(16) /*!< pin G4P0 analog switch state */
#define TSI_ASW_G4P1 BIT(17) /*!< pin G4P1 analog switch state */
#define TSI_ASW_G4P2 BIT(18) /*!< pin G4P2 analog switch state */
#define TSI_ASW_G4P3 BIT(19) /*!< pin G4P3 analog switch state */
#define TSI_ASW_G5P0 BIT(20) /*!< pin G5P0 analog switch state */
#define TSI_ASW_G5P1 BIT(21) /*!< pin G5P1 analog switch state */
#define TSI_ASW_G5P2 BIT(22) /*!< pin G5P2 analog switch state */
#define TSI_ASW_G5P3 BIT(23) /*!< pin G5P3 analog switch state */
/* TSI_SAMPCFG */
#define TSI_SAMPCFG_G0P0 BIT(0) /*!< pin G0P0 sample pin mode */
#define TSI_SAMPCFG_G0P1 BIT(1) /*!< pin G0P1 sample pin mode */
#define TSI_SAMPCFG_G0P2 BIT(2) /*!< pin G0P2 sample pin mode */
#define TSI_SAMPCFG_G0P3 BIT(3) /*!< pin G0P3 sample pin mode */
#define TSI_SAMPCFG_G1P0 BIT(4) /*!< pin G1P0 sample pin mode */
#define TSI_SAMPCFG_G1P1 BIT(5) /*!< pin G1P1 sample pin mode */
#define TSI_SAMPCFG_G1P2 BIT(6) /*!< pin G1P2 sample pin mode */
#define TSI_SAMPCFG_G1P3 BIT(7) /*!< pin G1P3 sample pin mode */
#define TSI_SAMPCFG_G2P0 BIT(8) /*!< pin G2P0 sample pin mode */
#define TSI_SAMPCFG_G2P1 BIT(9) /*!< pin G2P1 sample pin mode */
#define TSI_SAMPCFG_G2P2 BIT(10) /*!< pin G2P2 sample pin mode */
#define TSI_SAMPCFG_G2P3 BIT(11) /*!< pin G2P3 sample pin mode */
#define TSI_SAMPCFG_G3P0 BIT(12) /*!< pin G3P0 sample pin mode */
#define TSI_SAMPCFG_G3P1 BIT(13) /*!< pin G3P1 sample pin mode */
#define TSI_SAMPCFG_G3P2 BIT(14) /*!< pin G3P2 sample pin mode */
#define TSI_SAMPCFG_G3P3 BIT(15) /*!< pin G3P3 sample pin mode */
#define TSI_SAMPCFG_G4P0 BIT(16) /*!< pin G4P0 sample pin mode */
#define TSI_SAMPCFG_G4P1 BIT(17) /*!< pin G4P1 sample pin mode */
#define TSI_SAMPCFG_G4P2 BIT(18) /*!< pin G4P2 sample pin mode */
#define TSI_SAMPCFG_G4P3 BIT(19) /*!< pin G4P3 sample pin mode */
#define TSI_SAMPCFG_G5P0 BIT(20) /*!< pin G5P0 sample pin mode */
#define TSI_SAMPCFG_G5P1 BIT(21) /*!< pin G5P1 sample pin mode */
#define TSI_SAMPCFG_G5P2 BIT(22) /*!< pin G5P2 sample pin mode */
#define TSI_SAMPCFG_G5P3 BIT(23) /*!< pin G5P3 sample pin mode */
/* TSI_CHCFG */
#define TSI_CHCFG_G0P0 BIT(0) /*!< pin G0P0 channel pin mode */
#define TSI_CHCFG_G0P1 BIT(1) /*!< pin G0P1 channel pin mode */
#define TSI_CHCFG_G0P2 BIT(2) /*!< pin G0P2 channel pin mode */
#define TSI_CHCFG_G0P3 BIT(3) /*!< pin G0P3 channel pin mode */
#define TSI_CHCFG_G1P0 BIT(4) /*!< pin G1P0 channel pin mode */
#define TSI_CHCFG_G1P1 BIT(5) /*!< pin G1P1 channel pin mode */
#define TSI_CHCFG_G1P2 BIT(6) /*!< pin G1P2 channel pin mode */
#define TSI_CHCFG_G1P3 BIT(7) /*!< pin G1P3 channel pin mode */
#define TSI_CHCFG_G2P0 BIT(8) /*!< pin G2P0 channel pin mode */
#define TSI_CHCFG_G2P1 BIT(9) /*!< pin G2P1 channel pin mode */
#define TSI_CHCFG_G2P2 BIT(10) /*!< pin G2P2 channel pin mode */
#define TSI_CHCFG_G2P3 BIT(11) /*!< pin G2P3 channel pin mode */
#define TSI_CHCFG_G3P0 BIT(12) /*!< pin G3P0 channel pin mode */
#define TSI_CHCFG_G3P1 BIT(13) /*!< pin G3P1 channel pin mode */
#define TSI_CHCFG_G3P2 BIT(14) /*!< pin G3P2 channel pin mode */
#define TSI_CHCFG_G3P3 BIT(15) /*!< pin G3P3 channel pin mode */
#define TSI_CHCFG_G4P0 BIT(16) /*!< pin G4P0 channel pin mode */
#define TSI_CHCFG_G4P1 BIT(17) /*!< pin G4P1 channel pin mode */
#define TSI_CHCFG_G4P2 BIT(18) /*!< pin G4P2 channel pin mode */
#define TSI_CHCFG_G4P3 BIT(19) /*!< pin G4P3 channel pin mode */
#define TSI_CHCFG_G5P0 BIT(20) /*!< pin G5P0 channel pin mode */
#define TSI_CHCFG_G5P1 BIT(21) /*!< pin G5P1 channel pin mode */
#define TSI_CHCFG_G5P2 BIT(22) /*!< pin G5P2 channel pin mode */
#define TSI_CHCFG_G5P3 BIT(23) /*!< pin G5P3 channel pin mode */
/* TSI_GCTL */
#define TSI_GCTL_GE0 BIT(0) /*!< group0 enable */
#define TSI_GCTL_GE1 BIT(1) /*!< group1 enable */
#define TSI_GCTL_GE2 BIT(2) /*!< group2 enable */
#define TSI_GCTL_GE3 BIT(3) /*!< group3 enable */
#define TSI_GCTL_GE4 BIT(4) /*!< group4 enable */
#define TSI_GCTL_GE5 BIT(5) /*!< group5 enable */
#define TSI_GCTL_GC0 BIT(16) /*!< group0 complete */
#define TSI_GCTL_GC1 BIT(17) /*!< group1 complete */
#define TSI_GCTL_GC2 BIT(18) /*!< group2 complete */
#define TSI_GCTL_GC3 BIT(19) /*!< group3 complete */
#define TSI_GCTL_GC4 BIT(20) /*!< group4 complete */
#define TSI_GCTL_GC5 BIT(21) /*!< group5 complete */
/* constants definitions */
/* CTCLK clock division factor */
#define CTL_CTCDIV(regval) (BITS(12,14) & ((regval) << 12U)) /*!< CTCLK clock division factor */
#define TSI_CTCDIV_DIV1 CTL_CTCDIV(0) /*!< fCTCLK = fHCLK */
#define TSI_CTCDIV_DIV2 CTL_CTCDIV(1) /*!< fCTCLK = fHCLK/2 */
#define TSI_CTCDIV_DIV4 CTL_CTCDIV(2) /*!< fCTCLK = fHCLK/4 */
#define TSI_CTCDIV_DIV8 CTL_CTCDIV(3) /*!< fCTCLK = fHCLK/8 */
#define TSI_CTCDIV_DIV16 CTL_CTCDIV(4) /*!< fCTCLK = fHCLK/16 */
#define TSI_CTCDIV_DIV32 CTL_CTCDIV(5) /*!< fCTCLK = fHCLK/32 */
#define TSI_CTCDIV_DIV64 CTL_CTCDIV(6) /*!< fCTCLK = fHCLK/64 */
#define TSI_CTCDIV_DIV128 CTL_CTCDIV(7) /*!< fCTCLK = fHCLK/128 */
/* charge transfer state duration Time */
#define CTL_CTDT(regval) (BITS(24,27) & ((regval) << 24U)) /*!< charge transfer state duration time */
#define TSI_TRANSFER_1CTCLK CTL_CTDT(0) /*!< the duration time of transfer state is 1 CTCLK */
#define TSI_TRANSFER_2CTCLK CTL_CTDT(1) /*!< the duration time of transfer state is 2 CTCLK */
#define TSI_TRANSFER_3CTCLK CTL_CTDT(2) /*!< the duration time of transfer state is 3 CTCLK */
#define TSI_TRANSFER_4CTCLK CTL_CTDT(3) /*!< the duration time of transfer state is 4 CTCLK */
#define TSI_TRANSFER_5CTCLK CTL_CTDT(4) /*!< the duration time of transfer state is 5 CTCLK */
#define TSI_TRANSFER_6CTCLK CTL_CTDT(5) /*!< the duration time of transfer state is 6 CTCLK */
#define TSI_TRANSFER_7CTCLK CTL_CTDT(6) /*!< the duration time of transfer state is 7 CTCLK */
#define TSI_TRANSFER_8CTCLK CTL_CTDT(7) /*!< the duration time of transfer state is 8 CTCLK */
#define TSI_TRANSFER_9CTCLK CTL_CTDT(8) /*!< the duration time of transfer state is 9 CTCLK */
#define TSI_TRANSFER_10CTCLK CTL_CTDT(9) /*!< the duration time of transfer state is 10 CTCLK */
#define TSI_TRANSFER_11CTCLK CTL_CTDT(10) /*!< the duration time of transfer state is 11 CTCLK */
#define TSI_TRANSFER_12CTCLK CTL_CTDT(11) /*!< the duration time of transfer state is 12 CTCLK */
#define TSI_TRANSFER_13CTCLK CTL_CTDT(12) /*!< the duration time of transfer state is 13 CTCLK */
#define TSI_TRANSFER_14CTCLK CTL_CTDT(13) /*!< the duration time of transfer state is 14 CTCLK */
#define TSI_TRANSFER_15CTCLK CTL_CTDT(14) /*!< the duration time of transfer state is 15 CTCLK */
#define TSI_TRANSFER_16CTCLK CTL_CTDT(15) /*!< the duration time of transfer state is 16 CTCLK */
/* charge state duration time */
#define CTL_CDT(regval) (BITS(28,31) & ((regval) << 28U)) /*!< charge state duration time */
#define TSI_CHARGE_1CTCLK CTL_CDT(0) /*!< the duration time of charge state is 1 CTCLK */
#define TSI_CHARGE_2CTCLK CTL_CDT(1) /*!< the duration time of charge state is 2 CTCLK */
#define TSI_CHARGE_3CTCLK CTL_CDT(2) /*!< the duration time of charge state is 3 CTCLK */
#define TSI_CHARGE_4CTCLK CTL_CDT(3) /*!< the duration time of charge state is 4 CTCLK */
#define TSI_CHARGE_5CTCLK CTL_CDT(4) /*!< the duration time of charge state is 5 CTCLK */
#define TSI_CHARGE_6CTCLK CTL_CDT(5) /*!< the duration time of charge state is 6 CTCLK */
#define TSI_CHARGE_7CTCLK CTL_CDT(6) /*!< the duration time of charge state is 7 CTCLK */
#define TSI_CHARGE_8CTCLK CTL_CDT(7) /*!< the duration time of charge state is 8 CTCLK */
#define TSI_CHARGE_9CTCLK CTL_CDT(8) /*!< the duration time of charge state is 9 CTCLK */
#define TSI_CHARGE_10CTCLK CTL_CDT(9) /*!< the duration time of charge state is 10 CTCLK */
#define TSI_CHARGE_11CTCLK CTL_CDT(10) /*!< the duration time of charge state is 11 CTCLK */
#define TSI_CHARGE_12CTCLK CTL_CDT(11) /*!< the duration time of charge state is 12 CTCLK */
#define TSI_CHARGE_13CTCLK CTL_CDT(12) /*!< the duration time of charge state is 13 CTCLK */
#define TSI_CHARGE_14CTCLK CTL_CDT(13) /*!< the duration time of charge state is 14 CTCLK */
#define TSI_CHARGE_15CTCLK CTL_CDT(14) /*!< the duration time of charge state is 15 CTCLK */
#define TSI_CHARGE_16CTCLK CTL_CDT(15) /*!< the duration time of charge state is 16 CTCLK */
/* max cycle number of a sequence */
#define CTL_MCN(regval) (BITS(5,7) & ((regval) << 5U)) /*!< max cycle number of a sequence */
#define TSI_MAXNUM255 CTL_MCN(0) /*!< the max cycle number of a sequence is 255 */
#define TSI_MAXNUM511 CTL_MCN(1) /*!< the max cycle number of a sequence is 511 */
#define TSI_MAXNUM1023 CTL_MCN(2) /*!< the max cycle number of a sequence is 1023 */
#define TSI_MAXNUM2047 CTL_MCN(3) /*!< the max cycle number of a sequence is 2047 */
#define TSI_MAXNUM4095 CTL_MCN(4) /*!< the max cycle number of a sequence is 4095 */
#define TSI_MAXNUM8191 CTL_MCN(5) /*!< the max cycle number of a sequence is 8191 */
#define TSI_MAXNUM16383 CTL_MCN(6) /*!< the max cycle number of a sequence is 16383 */
/* ECCLK clock division factor */
#define TSI_EXTEND_DIV1 ((uint32_t)0x00000000U) /*!< fECCLK = fHCLK */
#define TSI_EXTEND_DIV2 ((uint32_t)0x00000001U) /*!< fECCLK = fHCLK/2 */
/* Extend Charge State Maximum Duration Time */
#define TSI_EXTENDMAX(regval) (BITS(17,23) & ((regval) << 17U)) /* value range 1...128,extend charge state maximum duration time */
/* hardware trigger mode */
#define TSI_FALLING_TRIGGER ((uint32_t)0x00000000U) /*!< falling edge trigger TSI charge transfer sequence */
#define TSI_RISING_TRIGGER ((uint32_t)0x00000001U) /*!< rising edge trigger TSI charge transfer sequence */
/* pin mode */
#define TSI_OUTPUT_LOW ((uint32_t)0x00000000U) /*!< TSI pin will output low when IDLE */
#define TSI_INPUT_FLOATING ((uint32_t)0x00000001U) /*!< TSI pin will keep input_floating when IDLE */
/* interrupt enable bits */
#define TSI_INT_CTCF TSI_INTEN_CTCFIE /*!< charge transfer complete flag interrupt enable */
#define TSI_INTEN_MNERR TSI_INTEN_MNERRIE /*!< max cycle number error interrupt enable */
/* interrupt flag bits */
#define TSI_INT_FLAG_CTC TSI_INTF_CTCF /*!< charge transfer complete flag */
#define TSI_INT_FLAG_MNERR TSI_INTF_MNERR /*!< max cycle number error */
/* function declarations */
/* reset TSI peripheral */
void tsi_deinit(void);
/* initialize TSI plus prescaler,charge plus,transfer plus,max cycle number */
void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number);
/* enable TSI module */
void tsi_enable(void);
/* disable TSI module */
void tsi_disable(void);
/* enable sample pin */
void tsi_sample_pin_enable(uint32_t sample);
/* disable sample pin */
void tsi_sample_pin_disable(uint32_t sample);
/* enable channel pin */
void tsi_channel_pin_enable(uint32_t channel);
/* disable channel pin */
void tsi_channel_pin_disable(uint32_t channel);
/* configure TSI triggering by software */
void tsi_sofeware_mode_config(void);
/* start a charge-transfer sequence when TSI is in software trigger mode */
void tsi_software_start(void);
/* stop a charge-transfer sequence when TSI is in software trigger mode */
void tsi_software_stop(void);
/* configure TSI triggering by hardware */
void tsi_hardware_mode_config(uint8_t trigger_edge);
/* configure TSI pin mode when charge-transfer sequence is IDLE */
void tsi_pin_mode_config(uint8_t pin_mode);
/* configure extend charge state */
void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration);
/* configure charge plus and transfer plus */
void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration);
/* configure the max cycle number of a charge-transfer sequence */
void tsi_max_number_config(uint32_t max_number);
/* switch on hysteresis pin */
void tsi_hysteresis_on(uint32_t group_pin);
/* switch off hysteresis pin */
void tsi_hysteresis_off(uint32_t group_pin);
/* switch on analog pin */
void tsi_analog_on(uint32_t group_pin);
/* switch off analog pin */
void tsi_analog_off(uint32_t group_pin);
/* enable TSI interrupt */
void tsi_interrupt_enable(uint32_t source);
/* disable TSI interrupt */
void tsi_interrupt_disable(uint32_t source);
/* clear interrupt flag */
void tsi_interrupt_flag_clear(uint32_t flag);
/* get TSI module current status */
FlagStatus tsi_interrupt_flag_get(uint32_t status);
/* enbale group */
void tsi_group_enable(uint32_t group);
/* disbale group */
void tsi_group_disable(uint32_t group);
/* get group complete status */
FlagStatus tsi_group_status_get(uint32_t group);
/* get the cycle number for group0 as soon as a charge-transfer sequence completes */
uint16_t tsi_group0_cycle_get(void);
/* get the cycle number for group1 as soon as a charge-transfer sequence completes */
uint16_t tsi_group1_cycle_get(void);
/* get the cycle number for group2 as soon as a charge-transfer sequence completes */
uint16_t tsi_group2_cycle_get(void);
/* get the cycle number for group3 as soon as a charge-transfer sequence completes */
uint16_t tsi_group3_cycle_get(void);
/* get the cycle number for group4 as soon as a charge-transfer sequence completes */
uint16_t tsi_group4_cycle_get(void);
/* get the cycle number for group5 as soon as a charge-transfer sequence completes */
uint16_t tsi_group5_cycle_get(void);
#endif /* GD32F1X0_TSI_H */

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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_usart.h Normal file
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/*!
\file gd32f1x0_usart.h
\brief definitions for the USART
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_USART_H
#define GD32F1X0_USART_H
#include "gd32f1x0.h"
/* USARTx(x=0,1) definitions */
#define USART0 (USART_BASE + 0x0000F400U)
#define USART1 USART_BASE
/* registers definitions */
#define USART_CTL0(usartx) REG32((usartx) + 0x00U) /*!< USART control register 0 */
#define USART_CTL1(usartx) REG32((usartx) + 0x04U) /*!< USART control register 1 */
#define USART_CTL2(usartx) REG32((usartx) + 0x08U) /*!< USART control register 2 */
#define USART_BAUD(usartx) REG32((usartx) + 0x0CU) /*!< USART baud rate register */
#define USART_GP(usartx) REG32((usartx) + 0x10U) /*!< USART guard time and prescaler register */
#define USART_RT(usartx) REG32((usartx) + 0x14U) /*!< USART receiver timeout register */
#define USART_CMD(usartx) REG32((usartx) + 0x18U) /*!< USART command register */
#define USART_STAT(usartx) REG32((usartx) + 0x1CU) /*!< USART status register */
#define USART_INTC(usartx) REG32((usartx) + 0x20U) /*!< USART status clear register */
#define USART_RDATA(usartx) REG32((usartx) + 0x24U) /*!< USART receive data register */
#define USART_TDATA(usartx) REG32((usartx) + 0x28U) /*!< USART transmit data register */
/* bits definitions */
/* USARTx_CTL0 */
#define USART_CTL0_UEN BIT(0) /*!< USART enable */
#define USART_CTL0_UESM BIT(1) /*!< USART enable in deep-sleep mode */
#define USART_CTL0_REN BIT(2) /*!< receiver enable */
#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */
#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */
#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */
#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */
#define USART_CTL0_TBEIE BIT(7) /*!< transmitter register empty interrupt enable */
#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */
#define USART_CTL0_PM BIT(9) /*!< parity mode */
#define USART_CTL0_PCEN BIT(10) /*!< parity control enable */
#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */
#define USART_CTL0_WL BIT(12) /*!< word length */
#define USART_CTL0_MEN BIT(13) /*!< mute mode enable */
#define USART_CTL0_AMIE BIT(14) /*!< address match interrupt enable */
#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */
#define USART_CTL0_DED BITS(16,20) /*!< driver enable deassertion time */
#define USART_CTL0_DEA BITS(21,25) /*!< driver enable assertion time */
#define USART_CTL0_RTIE BIT(26) /*!< receiver timeout interrupt enable */
#define USART_CTL0_EBIE BIT(27) /*!< end of block interrupt enable */
/* USARTx_CTL1 */
#define USART_CTL1_ADDM BIT(4) /*!< address detection mode */
#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */
#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detection interrupt enable */
#define USART_CTL1_CLEN BIT(8) /*!< last bit clock pulse */
#define USART_CTL1_CPH BIT(9) /*!< clock phase */
#define USART_CTL1_CPL BIT(10) /*!< clock polarity */
#define USART_CTL1_CKEN BIT(11) /*!< ck pin enable */
#define USART_CTL1_STB BITS(12,13) /*!< stop bits length */
#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */
#define USART_CTL1_STRP BIT(15) /*!< swap TX/RX pins */
#define USART_CTL1_RINV BIT(16) /*!< RX pin level inversion */
#define USART_CTL1_TINV BIT(17) /*!< TX pin level inversion */
#define USART_CTL1_DINV BIT(18) /*!< data bit level inversion */
#define USART_CTL1_MSBF BIT(19) /*!< most significant bit first */
#define USART_CTL1_ABDEN BIT(20) /*!< auto baud rate enable */
#define USART_CTL1_ABDM BITS(21,22) /*!< auto baud rate mode */
#define USART_CTL1_RTEN BIT(23) /*!< receiver timeout enable */
#define USART_CTL1_ADDR BITS(24,31) /*!< address of the USART terminal */
/* USARTx_CTL2 */
#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable in multibuffer communication */
#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */
#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */
#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */
#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */
#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */
#define USART_CTL2_DENR BIT(6) /*!< DMA enable for reception */
#define USART_CTL2_DENT BIT(7) /*!< DMA enable for transmission */
#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */
#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */
#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */
#define USART_CTL2_OSB BIT(11) /*!< one sample bit mode */
#define USART_CTL2_OVRD BIT(12) /*!< overrun disable */
#define USART_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */
#define USART_CTL2_DEM BIT(14) /*!< driver enable mode */
#define USART_CTL2_DEP BIT(15) /*!< driver enable polarity mode */
#define USART_CTL2_SCRTNUM BITS(17,19) /*!< smartcard auto-retry number */
#define USART_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */
#define USART_CTL2_WUIE BIT(22) /*!< wakeup from deep-sleep mode interrupt enable */
/* USARTx_BAUD */
#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction of baud-rate divider */
#define USART_BAUD_INTDIV BITS(4,15) /*!< integer of baud-rate divider */
/* USARTx_GP */
#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */
#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */
/* USARTx_RT */
#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */
#define USART_RT_BL BITS(24,31) /*!< block length */
/* USARTx_CMD */
#define USART_CMD_ABDCMD BIT(0) /*!< auto baudrate detection command */
#define USART_CMD_SBKCMD BIT(1) /*!< send break command */
#define USART_CMD_MMCMD BIT(2) /*!< mute mode command */
#define USART_CMD_RXFCMD BIT(3) /*!< receive data flush command */
#define USART_CMD_TXFCMD BIT(4) /*!< transmit data flush request */
/* USARTx_STAT */
#define USART_STAT_PERR BIT(0) /*!< parity error flag */
#define USART_STAT_FERR BIT(1) /*!< frame error flag */
#define USART_STAT_NERR BIT(2) /*!< noise error flag */
#define USART_STAT_ORERR BIT(3) /*!< overrun error */
#define USART_STAT_IDLEF BIT(4) /*!< idle line detected flag */
#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */
#define USART_STAT_TC BIT(6) /*!< transmission completed */
#define USART_STAT_TBE BIT(7) /*!< transmit data register empty */
#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */
#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */
#define USART_STAT_CTS BIT(10) /*!< CTS level */
#define USART_STAT_RTF BIT(11) /*!< receiver timeout flag */
#define USART_STAT_EBF BIT(12) /*!< end of block flag */
#define USART_STAT_ABDE BIT(14) /*!< auto baudrate detection error */
#define USART_STAT_ABDF BIT(15) /*!< auto baudrate detection flag */
#define USART_STAT_BSY BIT(16) /*!< busy flag */
#define USART_STAT_AMF BIT(17) /*!< address match flag */
#define USART_STAT_SBF BIT(18) /*!< send break flag */
#define USART_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */
#define USART_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */
#define USART_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */
#define USART_STAT_REA BIT(22) /*!< receive enable acknowledge flag */
/* USARTx_INTC */
#define USART_INTC_PEC BIT(0) /*!< parity error clear */
#define USART_INTC_FEC BIT(1) /*!< frame error flag clear */
#define USART_INTC_NEC BIT(2) /*!< noise detected clear */
#define USART_INTC_OREC BIT(3) /*!< overrun error clear */
#define USART_INTC_IDLEC BIT(4) /*!< idle line detected clear */
#define USART_INTC_TCC BIT(6) /*!< transmission complete clear */
#define USART_INTC_LBDC BIT(8) /*!< LIN break detected clear */
#define USART_INTC_CTSC BIT(9) /*!< CTS change clear */
#define USART_INTC_RTC BIT(11) /*!< receiver timeout clear */
#define USART_INTC_EBC BIT(12) /*!< end of timeout clear */
#define USART_INTC_AMC BIT(17) /*!< address match clear */
#define USART_INTC_WUC BIT(20) /*!< wakeup from deep-sleep mode clear */
/* USARTx_RDATA */
#define USART_RDATA_RDATA BITS(0,8) /*!< receive data value */
/* USARTx_TDATA */
#define USART_TDATA_TDATA BITS(0,8) /*!< transmit data value */
/* constants definitions */
/* define the USART bit position and its register index offset */
#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
#define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
/* register offset */
#define USART_CTL0_REG_OFFSET 0x00U /*!< CTL0 register offset */
#define USART_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */
#define USART_CTL2_REG_OFFSET 0x08U /*!< CTL2 register offset */
#define USART_STAT_REG_OFFSET 0x1CU /*!< STAT register offset */
/* USART flags */
typedef enum{
/* flags in STAT register */
USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */
USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */
USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U), /*!< wakeup from Deep-sleep mode flag */
USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */
USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U), /*!< send break flag */
USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U), /*!< ADDR match flag */
USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U), /*!< busy flag */
USART_FLAG_ABD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 15U), /*!< auto baudrate detection flag */
USART_FLAG_ABDE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 14U), /*!< auto baudrate detection error */
USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U), /*!< end of block flag */
USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout flag */
USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U), /*!< CTS level */
USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */
USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */
USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */
USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */
USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */
USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */
USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */
USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */
USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */
USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */
}usart_flag_enum;
/* USART interrupt flags */
typedef enum
{
/* interrupt flags in CTL0 register */
USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U), /*!< end of block interrupt and flag */
USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout interrupt and flag */
USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U), /*!< address match interrupt and flag */
USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */
USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */
USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */
USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */
USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */
/* interrupt flags in CTL1 register */
USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */
/* interrupt flags in CTL2 register */
USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt and flag */
USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */
USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */
USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */
USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */
}usart_interrupt_flag_enum;
/* USART interrupt enable or disable */
typedef enum
{
/* interrupt in CTL0 register */
USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U), /*!< end of block interrupt */
USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U), /*!< receiver timeout interrupt */
USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U), /*!< address match interrupt */
USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */
USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */
USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */
USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */
/* interrupt in CTL1 register */
USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */
/* interrupt in CTL2 register */
USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */
USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */
USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */
}usart_interrupt_enum;
/* USART invert configure */
typedef enum {
/* data bit level inversion */
USART_DINV_ENABLE, /*!< data bit level inversion */
USART_DINV_DISABLE, /*!< data bit level not inversion */
/* TX pin level inversion */
USART_TXPIN_ENABLE, /*!< TX pin level inversion */
USART_TXPIN_DISABLE, /*!< TX pin level not inversion */
/* RX pin level inversion */
USART_RXPIN_ENABLE, /*!< RX pin level inversion */
USART_RXPIN_DISABLE, /*!< RX pin level not inversion */
/* swap TX/RX pins */
USART_SWAP_ENABLE, /*!< swap TX/RX pins */
USART_SWAP_DISABLE, /*!< not swap TX/RX pins */
}usart_invert_enum;
/* USART receiver configure */
#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */
#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */
/* USART transmitter configure */
#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */
#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */
/* USART parity bits definitions */
#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
#define USART_PM_NONE CTL0_PM(0) /*!< no parity */
#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */
#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */
/* USART wakeup method in mute mode */
#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11))
#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */
#define USART_WM_ADDR CTL0_WM(1) /*!< address match */
/* USART word length definitions */
#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12))
#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */
#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */
/* USART oversample mode */
#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15))
#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< oversampling by 8 */
#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< oversampling by 16 */
/* USART address detection mode */
#define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4))
#define USART_ADDM_4BIT CTL1_ADDM(0) /*!< 4-bit address detection */
#define USART_ADDM_FULLBIT CTL1_ADDM(1) /*!< full-bit address detection */
/* USART LIN break frame length */
#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5))
#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits break detection */
#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits break detection */
/* USART last bit clock pulse */
#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
#define USART_CLEN_NONE CTL1_CLEN(0) /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */
#define USART_CLEN_EN CTL1_CLEN(1) /*!< clock pulse of the last data bit (MSB) is output to the CK pin */
/* USART clock phase */
#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9))
#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */
#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */
/* USART clock polarity */
#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10))
#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */
#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */
/* USART stop bits definitions */
#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */
#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */
#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */
/* USART data is transmitted/received with the LSB/MSB first */
#define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19))
#define USART_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */
#define USART_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */
/* USART auto baud rate detection mode bits definitions */
#define CTL1_ABDM(regval) (BITS(21,22) & ((uint32_t)(regval) << 21))
#define USART_ABDM_FTOR CTL1_ABDM(0) /*!< falling edge to rising edge measurement */
#define USART_ABDM_FTOF CTL1_ABDM(1) /*!< falling edge to falling edge measurement */
/* USART IrDA low-power enable */
#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */
#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */
/* DMA enable for reception */
#define CTL2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6))
#define USART_DENR_ENABLE CTL2_DENR(1) /*!< enable for reception */
#define USART_DENR_DISABLE CTL2_DENR(0) /*!< disable for reception */
/* DMA enable for transmission */
#define CTL2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
#define USART_DENT_ENABLE CTL2_DENT(1) /*!< enable for transmission */
#define USART_DENT_DISABLE CTL2_DENT(0) /*!< disable for transmission */
/* USART RTS hardware flow control configure */
#define CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
#define USART_RTS_ENABLE CTL2_RTSEN(1) /*!< RTS hardware flow control enabled */
#define USART_RTS_DISABLE CTL2_RTSEN(0) /*!< RTS hardware flow control disabled */
/* USART CTS hardware flow control configure */
#define CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
#define USART_CTS_ENABLE CTL2_CTSEN(1) /*!< CTS hardware flow control enabled */
#define USART_CTS_DISABLE CTL2_CTSEN(0) /*!< CTS hardware flow control disabled */
/* USART one sample bit method configure */
#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11))
#define USART_OSB_1BIT CTL2_OSB(1) /*!< 1 sample bit */
#define USART_OSB_3BIT CTL2_OSB(0) /*!< 3 sample bits */
/* USART driver enable polarity mode */
#define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15))
#define USART_DEP_HIGH CTL2_DEP(0) /*!< DE signal is active high */
#define USART_DEP_LOW CTL2_DEP(1) /*!< DE signal is active low */
/* USART wakeup mode from deep-sleep mode */
#define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
#define USART_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */
#define USART_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */
#define USART_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */
/* function declarations */
/* initialization functions */
/* reset USART */
void usart_deinit(uint32_t usart_periph);
/* configure USART baud rate value */
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
/* configure USART parity function */
void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
/* configure USART word length */
void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
/* configure USART stop bit length */
void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
/* USART normal mode communication */
/* enable USART */
void usart_enable(uint32_t usart_periph);
/* disable USART */
void usart_disable(uint32_t usart_periph);
/* configure USART transmitter */
void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
/* configure USART receiver */
void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
/* USART transmit data function */
void usart_data_transmit(uint32_t usart_periph, uint32_t data);
/* USART receive data function */
uint16_t usart_data_receive(uint32_t usart_periph);
/* data is transmitted/received with the LSB/MSB first */
void usart_data_first_config(uint32_t usart_periph, uint32_t msbf);
/* configure USART inverted */
void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara);
/* overrun function is enabled */
void usart_overrun_enable(uint32_t usart_periph);
/* overrun function is disabled */
void usart_overrun_disable(uint32_t usart_periph);
/* configure the USART oversample mode */
void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp);
/* sample bit method configure */
void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb);
/* auto baud rate detection */
/* auto baud rate detection enable */
void usart_autobaud_detection_enable(uint32_t usart_periph);
/* auto baud rate detection disable */
void usart_autobaud_detection_disable(uint32_t usart_periph);
/* auto baud rate detection mode configure */
void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod);
/* multi-processor communication */
/* enable mute mode */
void usart_mute_mode_enable(uint32_t usart_periph);
/* disable mute mode */
void usart_mute_mode_disable(uint32_t usart_periph);
/* configure wakeup method in mute mode */
void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod);
/* address detection mode configure */
void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod);
/* configure address of the USART */
void usart_address_config(uint32_t usart_periph, uint8_t addr);
/* enable receiver timeout */
void usart_receiver_timeout_enable(uint32_t usart_periph);
/* disable receiver timeout */
void usart_receiver_timeout_disable(uint32_t usart_periph);
/* configure receiver timeout threshold */
void usart_receiver_timeout_config(uint32_t usart_periph, uint32_t rtimeout);
/* LIN mode communication */
/* LIN mode enable */
void usart_lin_mode_enable(uint32_t usart_periph);
/* LIN mode disable */
void usart_lin_mode_disable(uint32_t usart_periph);
/* LIN break detection length */
void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen);
/* half-duplex communication */
/* half-duplex enable */
void usart_halfduplex_enable(uint32_t usart_periph);
/* half-duplex disable */
void usart_halfduplex_disable(uint32_t usart_periph);
/* synchronous communication */
/* clock enable */
void usart_clock_enable(uint32_t usart_periph);
/* clock disable*/
void usart_clock_disable(uint32_t usart_periph);
/* configure USART synchronous mode parameters */
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
/* smartcard communication */
/* smartcard mode enable */
void usart_smartcard_mode_enable(uint32_t usart_periph);
/* smartcard mode disable */
void usart_smartcard_mode_disable(uint32_t usart_periph);
/* NACK enable in smartcard mode */
void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
/* NACK disable in smartcard mode */
void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
/* guard time value configure in smartcard mode */
void usart_guard_time_config(uint32_t usart_periph, uint32_t guat);
/* block length configure */
void usart_block_length_config(uint32_t usart_periph, uint32_t bl);
/* smartcard auto-retry number configure */
void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum);
/* IrDA communication */
/* enable IrDA mode */
void usart_irda_mode_enable(uint32_t usart_periph);
/* disable IrDA mode */
void usart_irda_mode_disable(uint32_t usart_periph);
/* configure IrDA low-power */
void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
/* configure the peripheral clock prescaler */
void usart_prescaler_config(uint32_t usart_periph, uint32_t psc);
/* hardware flow communication */
/* configure hardware flow control RTS */
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
/* configure hardware flow control CTS */
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
/* RS485 driver enable */
void usart_rs485_driver_enable(uint32_t usart_periph);
/* RS485 driver disable */
void usart_rs485_driver_disable(uint32_t usart_periph);
/* driver enable assertion time configure */
void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime);
/* driver enable de-assertion time configure */
void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime);
/* configure driver enable polarity mode */
void usart_depolarity_config(uint32_t usart_periph, uint32_t dep);
/* USART DMA */
/* configure USART DMA for reception */
void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd);
/* configure USART DMA for transmission */
void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd);
/* disable DMA on reception error */
void usart_reception_error_dma_disable(uint32_t usart_periph);
/* enable DMA on reception error */
void usart_reception_error_dma_enable(uint32_t usart_periph);
/* USART be able to wake up the mcu from deep-sleep mode */
void usart_wakeup_enable(uint32_t usart_periph);
/* USART be not able to wake up the mcu from deep-sleep mode */
void usart_wakeup_disable(uint32_t usart_periph);
/* wakeup mode from deep-sleep mode */
void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum);
/* flag functions */
/* get flag in STAT register */
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
/* clear flag in STAT register */
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
/* enable USART interrupt */
void usart_interrupt_enable(uint32_t usart_periph, uint32_t inttype);
/* disable USART interrupt */
void usart_interrupt_disable(uint32_t usart_periph, uint32_t inttype);
/* enable USART command */
void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype);
/* get USART interrupt and flag status */
FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag);
/* clear interrupt flag in STAT register */
void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag);
#endif /* GD32F1X0_USART_H */

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Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_wwdgt.h Normal file
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/*!
\file gd32f1x0_wwdgt.h
\brief definitions for the WWDGT
*/
/*
Copyright (C) 2017 GigaDevice
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
*/
#ifndef GD32F1X0_WWDGT_H
#define GD32F1X0_WWDGT_H
#include "gd32f1x0.h"
/* WWDGT definitions */
#define WWDGT WWDGT_BASE
/* registers definitions */
#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */
#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */
#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */
/* bits definitions */
/* WWDGT_CTL */
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
/* WWDGT_CFG */
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */
/* WWDGT_STAT */
#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */
/* constants definitions */
/* ctl register value */
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CTL_CNT bit field */
/* cfg register value */
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CFG_WIN bit field */
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */
#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
/* function declarations */
/* reset the window watchdog timer configuration */
void wwdgt_deinit(void);
/* start the window watchdog timer counter */
void wwdgt_enable(void);
/* configure the window watchdog timer counter value */
void wwdgt_counter_update(uint16_t counter_value);
/* configure counter value, window value, and prescaler divider value */
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
/* enable early wakeup interrupt of WWDGT */
void wwdgt_interrupt_enable(void);
/* check early wakeup interrupt state of WWDGT */
FlagStatus wwdgt_flag_get(void);
/* clear early wakeup interrupt state of WWDGT */
void wwdgt_flag_clear(void);
#endif /* GD32F1X0_WWDGT_H */