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Initial commit
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EmanuelFeru
116
Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_dbg.h
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116
Drivers/GD32F1x0_standard_peripheral/Include/gd32f1x0_dbg.h
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/*!
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\file gd32f1x0_dbg.h
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\brief definitions for the DBG
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*/
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/*
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Copyright (C) 2017 GigaDevice
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2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
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2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
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2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
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2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
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*/
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#ifndef GD32F1X0_DBG_H
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#define GD32F1X0_DBG_H
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#include "gd32f1x0.h"
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/* DBG definitions */
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#define DBG DBG_BASE
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/* registers definitions */
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#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
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#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */
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#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */
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/* bits definitions */
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/* DBG_ID */
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#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
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/* DBG_CTL0 */
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#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
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#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
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#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
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#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
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#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
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#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< TIMER0 counter kept when core is halted */
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#define DBG_CTL0_TIMER1_HOLD BIT(11) /*!< TIMER1 counter kept when core is halted */
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#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< TIMER2 counter kept when core is halted */
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#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
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#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
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#define DBG_CTL0_I2C2_HOLD BIT(17) /*!< hold I2C2 smbus when core is halted */
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#ifdef GD32F170_190
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#define DBG_CTL0_CAN0_HOLD BIT(18) /*!< CAN0 counter kept when core is halted */
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#endif /* GD32F170_190 */
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#define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
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#ifdef GD32F170_190
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#define DBG_CTL0_CAN1_HOLD BIT(21) /*!< hold CAN1 counter when core is halted */
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#endif /* GD32F170_190 */
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#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */
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/* DBG_CTL1 */
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#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */
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#define DBG_CTL1_TIMER14_HOLD BIT(16) /*!< hold TIMER14 counter when core is halted */
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#define DBG_CTL1_TIMER15_HOLD BIT(17) /*!< hold TIMER15 counter when core is halted */
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#define DBG_CTL1_TIMER16_HOLD BIT(18) /*!< hold TIMER16 counter when core is halted */
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/* constants definitions */
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#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
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#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
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#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
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/* define the peripheral debug hold bit position and its register index offset */
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#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
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#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
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#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
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/* register index */
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enum dbg_reg_idx
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{
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DBG_IDX_CTL0 = 0x04U,
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DBG_IDX_CTL1 = 0x08U,
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};
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/* peripherals hold bit */
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typedef enum
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{
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DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< FWDGT hold bit */
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DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< WWDGT hold bit */
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DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< TIMER0 hold bit */
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DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 11U), /*!< TIMER1 hold bit */
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DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< TIMER2 hold bit */
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#ifdef GD32F170_190
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DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 14U), /*!< CAN0 hold bit */
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#endif /* GD32F170_190 */
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DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< I2C0 hold bit */
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DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< I2C1 hold bit */
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DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 17U), /*!< I2C2 hold bit */
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DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< TIMER5 hold bit */
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#ifdef GD32F170_190
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DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 21U), /*!< CAN1 hold bit */
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#endif /* GD32F170_190 */
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DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< TIMER13 hold bit */
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DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< RTC hold bit */
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DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< TIMER14 hold bit */
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DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< TIMER15 hold bit */
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DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), /*!< TIMER16 hold bit */
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}dbg_periph_enum;
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/* function declarations */
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/* deinitialize the DBG */
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void dbg_deinit(void);
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/* read DBG_ID code register */
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uint32_t dbg_id_get(void);
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/* enable low power behavior when the MCU is in debug mode */
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void dbg_low_power_enable(uint32_t dbg_low_power);
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/* disable low power behavior when the MCU is in debug mode */
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void dbg_low_power_disable(uint32_t dbg_low_power);
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/* enable peripheral behavior when the MCU is in debug mode */
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void dbg_periph_enable(dbg_periph_enum dbg_periph);
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/* disable peripheral behavior when the MCU is in debug mode */
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void dbg_periph_disable(dbg_periph_enum dbg_periph);
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#endif /* GD32F1X0_DBG_H */
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