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106
Drivers/GD32F1x0_standard_peripheral/Source/gd32f1x0_dbg.c
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106
Drivers/GD32F1x0_standard_peripheral/Source/gd32f1x0_dbg.c
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/*!
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\file gd32f1x0_dbg.c
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\brief DBG driver
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*/
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/*
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Copyright (C) 2017 GigaDevice
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2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
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2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
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2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
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2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
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*/
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#include "gd32f1x0_dbg.h"
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#define DBG_RESET_VAL 0x00000000U
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/*!
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\brief deinitialize the DBG
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dbg_deinit(void)
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{
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DBG_CTL0 = DBG_RESET_VAL;
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DBG_CTL1 = DBG_RESET_VAL;
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}
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/*!
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\brief read DBG_ID code register
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\param[in] none
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\param[out] none
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\retval DBG_ID code
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*/
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uint32_t dbg_id_get(void)
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{
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return DBG_ID;
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}
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/*!
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\brief enable low power behavior when the mcu is in debug mode
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\param[in] dbg_low_power:
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this parameter can be any combination of the following values:
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\arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
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\arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
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\arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
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\param[out] none
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\retval none
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*/
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void dbg_low_power_enable(uint32_t dbg_low_power)
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{
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DBG_CTL0 |= dbg_low_power;
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}
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/*!
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\brief disable low power behavior when the mcu is in debug mode
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\param[in] dbg_low_power:
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this parameter can be any combination of the following values:
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\arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
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\arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
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\arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
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\param[out] none
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\retval none
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*/
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void dbg_low_power_disable(uint32_t dbg_low_power)
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{
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DBG_CTL0 &= ~dbg_low_power;
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}
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/*!
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\brief enable peripheral behavior when the mcu is in debug mode
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\param[in] dbg_periph: refer to dbg_periph_enum
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only one parameter can be selected which is shown as below:
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\arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
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\arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
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\arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted(170_190 series only)
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\arg DBG_I2Cx_HOLD (x=0,1,2): hold I2Cx smbus when core is halted
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\arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16): hold TIMERx counter when core is halted
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\arg DBG_RTC_HOLD : hold RTC calendar and wakeup counter when core is halted
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\param[out] none
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\retval none
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*/
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void dbg_periph_enable(dbg_periph_enum dbg_periph)
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{
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DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
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}
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/*!
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\brief disable peripheral behavior when the mcu is in debug mode
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\param[in] dbg_periph: refer to dbg_periph_enum
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only one parameter can be selected which is shown as below:
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\arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
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\arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
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\arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted(170_190 series only)
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\arg DBG_I2Cx_HOLD (x=0,1,2): hold I2Cx smbus when core is halted
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\arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16): hold TIMERx counter when core is halted
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\arg DBG_RTC_HOLD : hold RTC calendar and wakeup counter when core is halted
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\param[out] none
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\retval none
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*/
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void dbg_periph_disable(dbg_periph_enum dbg_periph)
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{
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DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
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}
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