mirror of
https://github.com/EFeru/hoverboard-sideboard-hack-GD.git
synced 2025-08-18 09:36:11 +00:00
Initial commit
This commit is contained in:
EmanuelFeru
492
Drivers/GD32F1x0_standard_peripheral/Source/gd32f1x0_dma.c
Normal file
492
Drivers/GD32F1x0_standard_peripheral/Source/gd32f1x0_dma.c
Normal file
@@ -0,0 +1,492 @@
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/*!
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\file gd32f1x0_dma.c
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\brief DMA driver
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*/
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/*
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Copyright (C) 2017 GigaDevice
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2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
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2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
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2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
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2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
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*/
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#include "gd32f1x0_dma.h"
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/*!
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\brief deinitialize DMA a channel registers
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\param[in] channelx: specify which DMA channel is deinitialized
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\arg DMA_CHx(x=0..6)
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\param[out] none
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\retval none
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*/
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void dma_deinit(dma_channel_enum channelx)
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{
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/* disable DMA a channel */
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
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/* reset DMA channel registers */
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DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE;
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DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE;
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DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE;
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DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE;
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DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx);
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}
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/*!
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\brief initialize DMA channel
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\param[in] channelx: specify which DMA channel is initialized
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\arg DMA_CHx(x=0..6)
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\param[in] init_struct: the data needed to initialize DMA channel
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periph_addr: peripheral base address
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periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT
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periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE
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memory_addr: memory base address
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memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT
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memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE
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direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL
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number: the number of remaining data to be transferred by the DMA
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priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH
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\param[out] none
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\retval none
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*/
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void dma_init(dma_channel_enum channelx, dma_parameter_struct init_struct)
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{
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uint32_t ctl;
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/* configure peripheral base address */
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DMA_CHPADDR(channelx) = init_struct.periph_addr;
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/* configure memory base address */
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DMA_CHMADDR(channelx) = init_struct.memory_addr;
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/* configure the number of remaining data to be transferred */
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DMA_CHCNT(channelx) = init_struct.number;
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/* configure peripheral transfer width,memory transfer width, */
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ctl = DMA_CHCTL(channelx);
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ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
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ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority);
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DMA_CHCTL(channelx)=ctl;
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/* configure peripheral increasing mode */
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if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){
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DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
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}else{
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
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}
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/* configure memory increasing mode */
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if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){
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DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
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}else{
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
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}
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/* configure the direction of data transfer */
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if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
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}else{
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DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
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}
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}
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/*!
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\brief enable DMA circulation mode
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\param[in] channelx: specify which DMA channel
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\arg DMA_CHx(x=0..6)
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\param[out] none
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\retval none
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*/
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void dma_circulation_enable(dma_channel_enum channelx)
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{
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DMA_CHCTL(channelx) |= DMA_CHXCTL_CMEN;
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}
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/*!
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\brief disable DMA circulation mode
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\param[in] channelx: specify which DMA channel
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\arg DMA_CHx(x=0..6)
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\param[out] none
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\retval none
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*/
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void dma_circulation_disable(dma_channel_enum channelx)
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{
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CMEN;
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}
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/*!
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\brief enable memory to memory mode
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\param[in] channelx: specify which DMA channel
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\arg DMA_CHx(x=0..6)
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\param[out] none
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\retval none
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*/
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void dma_memory_to_memory_enable(dma_channel_enum channelx)
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{
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DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M;
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}
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/*!
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\brief disable memory to memory mode
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\param[in] channelx: specify which DMA channel
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\arg DMA_CHx(x=0..6)
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\param[out] none
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\retval none
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*/
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void dma_memory_to_memory_disable(dma_channel_enum channelx)
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{
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M;
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}
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/*!
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\brief enable DMA channel
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\param[in] channelx: specify which DMA channel
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\arg DMA_CHx(x=0..6)
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\param[out] none
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\retval none
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*/
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void dma_channel_enable(dma_channel_enum channelx)
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{
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DMA_CHCTL(channelx) |= DMA_CHXCTL_CHEN;
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}
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/*!
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\brief disable DMA channel
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\param[in] channelx: specify which DMA channel
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\arg DMA_CHx(x=0..6)
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\param[out] none
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\retval none
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*/
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void dma_channel_disable(dma_channel_enum channelx)
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{
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
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}
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/*!
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\brief set DMA peripheral base address
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\param[in] channelx: specify which DMA channel to set peripheral base address
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\arg DMA_CHx(x=0..6)
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\param[in] address: peripheral base address
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\param[out] none
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\retval none
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*/
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void dma_periph_address_config(dma_channel_enum channelx, uint32_t address)
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{
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DMA_CHPADDR(channelx) = address;
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}
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/*!
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\brief set DMA Memory base address
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\param[in] channelx: specify which DMA channel to set Memory base address
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\arg DMA_CHx(x=0..6)
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\param[in] address: Memory base address
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\param[out] none
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\retval none
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*/
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void dma_memory_address_config(dma_channel_enum channelx, uint32_t address)
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{
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DMA_CHMADDR(channelx) = address;
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}
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/*!
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\brief set the number of remaining data to be transferred by the DMA
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\param[in] channelx: specify which DMA channel to set number
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\arg DMA_CHx(x=0..6)
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\param[in] number: the number of remaining data to be transferred by the DMA
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\param[out] none
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\retval none
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*/
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void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number)
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{
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DMA_CHCNT(channelx) = number;
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}
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/*!
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\brief get the number of remaining data to be transferred by the DMA
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\param[in] channelx: specify which DMA channel to set number
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\arg DMA_CHx(x=0..6)
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\param[out] none
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\retval uint32_t: the number of remaining data to be transferred by the DMA
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*/
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uint32_t dma_transfer_number_get(dma_channel_enum channelx)
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{
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return (uint32_t)DMA_CHCNT(channelx);
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}
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/*!
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\brief configure priority level of DMA channel
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\param[in] channelx: specify which DMA channel
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\arg DMA_CHx(x=0..6)
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\param[in] priority: priority Level of this channel
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\arg DMA_PRIORITY_LOW: low priority
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\arg DMA_PRIORITY_MEDIUM: medium priority
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\arg DMA_PRIORITY_HIGH: high priority
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\arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority
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\param[out] none
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\retval none
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*/
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void dma_priority_config(dma_channel_enum channelx, uint32_t priority)
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{
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uint32_t ctl;
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/* acquire DMA_CHxCTL register */
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ctl = DMA_CHCTL(channelx);
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/* assign regiser */
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ctl &= ~DMA_CHXCTL_PRIO;
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ctl |= priority;
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DMA_CHCTL(channelx) = ctl;
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}
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/*!
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\brief configure transfer data size of memory
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\param[in] channelx: specify which DMA channel
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\arg DMA_CHx(x=0..6)
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\param[in] msize: transfer data size of memory
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\arg DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit
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\arg DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit
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\arg DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit
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\param[out] none
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\retval none
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*/
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void dma_memory_width_config (dma_channel_enum channelx, uint32_t msize)
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{
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uint32_t ctl;
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/* acquire DMA_CHxCTL register */
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ctl = DMA_CHCTL(channelx);
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/* assign regiser */
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ctl &= ~DMA_CHXCTL_MWIDTH;
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ctl |= msize;
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DMA_CHCTL(channelx) = ctl;
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}
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/*!
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\brief configure transfer data size of peripheral
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\param[in] channelx: specify which DMA channel
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\arg DMA_CHx(x=0..6)
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\param[in] msize: transfer data size of peripheral
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\arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit
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\arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit
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\arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit
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\param[out] none
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\retval none
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*/
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void dma_periph_width_config (dma_channel_enum channelx, uint32_t psize)
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{
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uint32_t ctl;
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/* acquire DMA_CHxCTL register */
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ctl = DMA_CHCTL(channelx);
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/* assign regiser */
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ctl &= ~DMA_CHXCTL_PWIDTH;
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ctl |= psize;
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DMA_CHCTL(channelx) = ctl;
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}
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/*!
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\brief enable next address increasement algorithm of memory
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\param[in] channelx: specify which DMA channel
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\arg DMA_CHx(x=0..6)
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\param[out] none
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\retval none
|
||||
*/
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void dma_memory_increase_enable(dma_channel_enum channelx)
|
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{
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DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
|
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}
|
||||
|
||||
/*!
|
||||
\brief disable next address increasement algorithm of memory
|
||||
\param[in] channelx: specify which DMA channel
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\arg DMA_CHx(x=0..6)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dma_memory_increase_disable(dma_channel_enum channelx)
|
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{
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
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}
|
||||
|
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/*!
|
||||
\brief enable next address increasement algorithm of peripheral
|
||||
\param[in] channelx: specify which DMA channel
|
||||
\arg DMA_CHx(x=0..6)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dma_periph_increase_enable(dma_channel_enum channelx)
|
||||
{
|
||||
DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable next address increasement algorithm of peripheral
|
||||
\param[in] channelx: specify which DMA channel
|
||||
\arg DMA_CHx(x=0..6)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dma_periph_increase_disable(dma_channel_enum channelx)
|
||||
{
|
||||
DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the direction of data transfer on the channel
|
||||
\param[in] channelx: specify which DMA channel
|
||||
\arg DMA_CHx(x=0..6)
|
||||
\param[in] direction: specify the direction of data transfer
|
||||
\arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
|
||||
\arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dma_transfer_direction_config(dma_channel_enum channelx, uint8_t direction)
|
||||
{
|
||||
if(DMA_PERIPHERAL_TO_MEMORY == direction){
|
||||
DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
|
||||
} else {
|
||||
DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief check DMA flag and interrupt enable bit is set or not
|
||||
\param[in] channelx: specify which DMA channel to get flag
|
||||
\arg DMA_CHx(x=0..6)
|
||||
\param[in] flag: specify get which flag
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg DMA_INT_FLAG_G: global interrupt flag of channel
|
||||
\arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
|
||||
\arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
|
||||
\arg DMA_INT_FLAG_ERR: error interrupt flag of channel
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag)
|
||||
{
|
||||
uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
|
||||
uint32_t gif_check = 0x0FU, gif_enable = 0x0EU;
|
||||
|
||||
switch(flag){
|
||||
case DMA_INT_FLAG_FTF:
|
||||
interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
|
||||
interrupt_flag = interrupt_flag >> ((channelx) * 4U);
|
||||
interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE;
|
||||
break;
|
||||
case DMA_INT_FLAG_HTF:
|
||||
interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
|
||||
interrupt_flag = interrupt_flag >> ((channelx) * 4U);
|
||||
interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE;
|
||||
break;
|
||||
case DMA_INT_FLAG_ERR:
|
||||
interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
|
||||
interrupt_flag = interrupt_flag >> ((channelx) * 4U);
|
||||
interrupt_enable = DMA_CHCTL( channelx) & DMA_CHXCTL_ERRIE;
|
||||
break;
|
||||
case DMA_INT_FLAG_G:
|
||||
interrupt_flag = DMA_INTF & DMA_FLAG_ADD(gif_check, channelx);
|
||||
interrupt_flag = interrupt_flag >> ((channelx) * 4U);
|
||||
interrupt_enable = DMA_CHCTL(channelx) & gif_enable;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if(interrupt_flag & interrupt_enable){
|
||||
return SET;
|
||||
}else{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear DMA a channel flag
|
||||
\param[in] channelx: specify which DMA channel to clear flag
|
||||
\arg DMA_CHx(x=0..6)
|
||||
\param[in] flag: specify get which flag
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg DMA_INT_FLAG_G: global interrupt flag of channel
|
||||
\arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
|
||||
\arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
|
||||
\arg DMA_INT_FLAG_ERR: error interrupt flag of channel
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag)
|
||||
{
|
||||
DMA_INTC |= DMA_FLAG_ADD(flag, channelx);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable DMA interrupt
|
||||
\param[in] channelx: specify which DMA channel
|
||||
\arg DMA_CHx(x=0..6)
|
||||
\param[in] source: specify which interrupt to enbale
|
||||
\arg DMA_INT_ERR: channel error interrupt
|
||||
\arg DMA_INT_HTF: channel transfer half complete interrupt
|
||||
\arg DMA_INT_FTF: channel transfer complete interrupt
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source)
|
||||
{
|
||||
DMA_CHCTL(channelx) |= source;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable DMA interrupt
|
||||
\param[in] channelx: specify which DMA channel
|
||||
\arg DMA_CHx(x=0..6)
|
||||
\param[in] source: specify which interrupt to disbale
|
||||
\arg DMA_INT_ERR: channel error interrupt
|
||||
\arg DMA_INT_HTF: channel transfer half complete interrupt
|
||||
\arg DMA_INT_FTF: for channel transfer complete interrupt
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source)
|
||||
{
|
||||
DMA_CHCTL(channelx) &= ~source;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief check DMA flag is set or not
|
||||
\param[in] channelx: specify which DMA channel to get flag
|
||||
\arg DMA_CHx(x=0..6)
|
||||
\param[in] flag: specify get which flag
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg DMA_FLAG_G: global interrupt flag of channel
|
||||
\arg DMA_FLAG_FTF: full transfer finish flag of channel
|
||||
\arg DMA_FLAG_HTF: half transfer finish flag of channel
|
||||
\arg DMA_FLAG_ERR: error flag of channel
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag)
|
||||
{
|
||||
FlagStatus reval;
|
||||
|
||||
if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))){
|
||||
reval = SET;
|
||||
}else{
|
||||
reval = RESET;
|
||||
}
|
||||
|
||||
return reval;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear DMA a channel flag
|
||||
\param[in] channelx: specify which DMA channel to clear flag
|
||||
\arg DMA_CHx(x=0..6)
|
||||
\param[in] flag: specify get which flag
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg DMA_FLAG_G: global interrupt flag of channel
|
||||
\arg DMA_FLAG_FTF: full transfer finish flag of channel
|
||||
\arg DMA_FLAG_HTF: half transfer finish flag of channel
|
||||
\arg DMA_FLAG_ERR: error flag of channel
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dma_flag_clear(dma_channel_enum channelx, uint32_t flag)
|
||||
{
|
||||
DMA_INTC |= DMA_FLAG_ADD(flag, channelx);
|
||||
}
|
||||
Reference in New Issue
Block a user