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https://github.com/EFeru/hoverboard-sideboard-hack-GD.git
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Initial commit
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EmanuelFeru
257
Drivers/GD32F1x0_standard_peripheral/Source/gd32f1x0_pmu.c
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257
Drivers/GD32F1x0_standard_peripheral/Source/gd32f1x0_pmu.c
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/*!
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\file gd32f1x0_pmu.c
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\brief PMU driver
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*/
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/*
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Copyright (C) 2017 GigaDevice
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2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
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2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
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2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
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2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
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*/
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#include "gd32f1x0_pmu.h"
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/*!
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\brief reset PMU register
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_deinit(void)
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{
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/* reset PMU */
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rcu_periph_reset_enable(RCU_PMURST);
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rcu_periph_reset_disable(RCU_PMURST);
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}
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/*!
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\brief select low voltage detector threshold
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\param[in] lvdt_n:
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\arg PMU_LVDT_0: voltage threshold is 2.2V (GD32F130_150) or 2.4V (GD32F170_190)
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\arg PMU_LVDT_1: voltage threshold is 2.3V (GD32F130_150) or 2.7V (GD32F170_190)
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\arg PMU_LVDT_2: voltage threshold is 2.4V (GD32F130_150) or 3.0V (GD32F170_190)
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\arg PMU_LVDT_3: voltage threshold is 2.5V (GD32F130_150) or 3.3V (GD32F170_190)
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\arg PMU_LVDT_4: voltage threshold is 2.6V (GD32F130_150) or 3.6V (GD32F170_190)
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\arg PMU_LVDT_5: voltage threshold is 2.7V (GD32F130_150) or 3.9V (GD32F170_190)
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\arg PMU_LVDT_6: voltage threshold is 2.8V (GD32F130_150) or 4.2V (GD32F170_190)
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\arg PMU_LVDT_7: voltage threshold is 2.9V (GD32F130_150) or 4.5V (GD32F170_190)
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\param[out] none
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\retval none
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*/
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void pmu_lvd_select(uint32_t lvdt_n)
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{
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/* disable LVD */
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PMU_CTL &= ~PMU_CTL_LVDEN;
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/* clear LVDT bits */
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PMU_CTL &= ~PMU_CTL_LVDT;
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/* set LVDT bits according to lvdt_n */
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PMU_CTL |= lvdt_n;
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/* enable LVD */
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PMU_CTL |= PMU_CTL_LVDEN;
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}
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/*!
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\brief PMU lvd disable
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_lvd_disable(void)
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{
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/* disable LVD */
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PMU_CTL &= ~PMU_CTL_LVDEN;
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}
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/*!
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\brief PMU work at sleep mode
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\param[in] sleepmodecmd:
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\arg WFI_CMD: use WFI command
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\arg WFE_CMD: use WFE command
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\param[out] none
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\retval none
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*/
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void pmu_to_sleepmode(uint8_t sleepmodecmd)
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{
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/* clear sleepdeep bit of Cortex-M3 system control register */
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SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
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/* select WFI or WFE command to enter sleep mode */
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if(WFI_CMD == sleepmodecmd){
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__WFI();
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}else{
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__WFE();
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}
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}
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/*!
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\brief PMU work at deepsleep mode
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\param[in] ldo
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\arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode
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\arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
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\param[in] deepsleepmodecmd:
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\arg WFI_CMD: use WFI command
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\arg WFE_CMD: use WFE command
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\param[out] none
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\retval none
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*/
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void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
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{
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static uint32_t reg_snap[ 4 ];
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/* clear stbmod and ldolp bits */
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PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
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/* set ldolp bit according to pmu_ldo */
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PMU_CTL |= ldo;
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/* set sleepdeep bit of Cortex-M3 system control register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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reg_snap[ 0 ] = REG32( 0xE000E010 );
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reg_snap[ 1 ] = REG32( 0xE000E100 );
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reg_snap[ 2 ] = REG32( 0xE000E104 );
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reg_snap[ 3 ] = REG32( 0xE000E108 );
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REG32( 0xE000E010 ) &= 0x00010004;
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REG32( 0xE000E180 ) = 0XB7FFEF19;
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REG32( 0xE000E184 ) = 0XFFFFFBFF;
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REG32( 0xE000E188 ) = 0xFFFFFFFF;
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/* select WFI or WFE command to enter deepsleep mode */
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if(WFI_CMD == deepsleepmodecmd){
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__WFI();
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}else{
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__SEV();
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__WFE();
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__WFE();
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}
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REG32( 0xE000E010 ) = reg_snap[ 0 ] ;
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REG32( 0xE000E100 ) = reg_snap[ 1 ] ;
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REG32( 0xE000E104 ) = reg_snap[ 2 ] ;
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REG32( 0xE000E108 ) = reg_snap[ 3 ] ;
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/* reset sleepdeep bit of Cortex-M3 system control register */
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SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
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}
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/*!
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\brief pmu work at standby mode
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\param[in] standbymodecmd:
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\arg WFI_CMD: use WFI command
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\arg WFE_CMD: use WFE command
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\param[out] none
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\retval none
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*/
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void pmu_to_standbymode(uint8_t standbymodecmd)
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{
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/* set sleepdeep bit of Cortex-M3 system control register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* set stbmod bit */
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PMU_CTL |= PMU_CTL_STBMOD;
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/* reset wakeup flag */
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PMU_CTL |= PMU_CTL_WURST;
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/* select WFI or WFE command to enter standby mode */
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if(WFI_CMD == standbymodecmd){
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__WFI();
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}else{
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__WFE();
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}
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}
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/*!
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\brief clear flag bit
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\param[in] flag_reset:
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\arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag
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\arg PMU_FLAG_RESET_STANDBY: reset standby flag
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\param[out] none
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\retval none
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*/
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void pmu_flag_clear(uint32_t flag_reset)
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{
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switch(flag_reset){
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case PMU_FLAG_RESET_WAKEUP:
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/* reset wakeup flag */
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PMU_CTL |= PMU_CTL_WURST;
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break;
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case PMU_FLAG_RESET_STANDBY:
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/* reset standby flag */
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PMU_CTL |= PMU_CTL_STBRST;
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break;
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default :
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break;
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}
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}
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/*!
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\brief get flag state
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\param[in] flag:
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\arg PMU_FLAG_WAKEUP: wakeup flag
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\arg PMU_FLAG_STANDBY: standby flag
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\arg PMU_FLAG_LVD: lvd flag
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\param[out] none
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\retval FlagStatus SET or RESET
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*/
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FlagStatus pmu_flag_get(uint32_t flag )
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{
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if(PMU_CS & flag){
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return SET;
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}else{
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return RESET;
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}
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}
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/*!
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\brief backup domain write enable
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_backup_write_enable(void)
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{
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PMU_CTL |= PMU_CTL_BKPWEN;
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}
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/*!
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\brief backup domain write disable
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_backup_write_disable(void)
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{
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PMU_CTL &= ~PMU_CTL_BKPWEN;
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}
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/*!
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\brief wakeup pin enable
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\param[in] wakeup_pin:
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\arg PMU_WAKEUP_PIN0: wakeup pin 0
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\arg PMU_WAKEUP_PIN1: wakeup pin 1
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\param[out] none
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\retval none
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*/
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void pmu_wakeup_pin_enable(uint32_t wakeup_pin )
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{
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PMU_CS |= wakeup_pin;
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}
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/*!
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\brief wakeup pin disable
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\param[in] wakeup_pin:
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\arg PMU_WAKEUP_PIN0: wakeup pin 0
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\arg PMU_WAKEUP_PIN1: wakeup pin 1
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\param[out] none
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\retval none
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*/
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void pmu_wakeup_pin_disable(uint32_t wakeup_pin )
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{
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PMU_CS &= ~wakeup_pin;
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}
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