Initial commit

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Analog_watchdog/gd32f1x0_it.c

@@ -0,0 +1,128 @@
+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+#include "gd32f1x0_eval.h"
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+}
+
+/*!
+    \brief      ADC and CMP handle function 
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void ADC_CMP_IRQHandler(void)
+{
+    /* clear the ADC interrupt or status flag */
+    adc_interrupt_flag_clear(ADC_FLAG_WDE);
+    /* turn on selected led */
+    gd_eval_led_on(LED2);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Analog_watchdog/gd32f1x0_it.h

@@ -0,0 +1,42 @@
+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* NMI handle function */
+void NMI_Handler(void);
+/* HardFault handle function */
+void HardFault_Handler(void);
+/* MemManage handle function */
+void MemManage_Handler(void);
+/* BusFault handle function */
+void BusFault_Handler(void);
+/* UsageFault handle function */
+void UsageFault_Handler(void);
+/* SVC handle function */
+void SVC_Handler(void);
+/* DebugMon handle function */
+void DebugMon_Handler(void);
+/* PendSV handle function */
+void PendSV_Handler(void);
+/* SysTick handle function */
+void SysTick_Handler(void);
+/* ADC and CMP handle function */
+void ADC_CMP_IRQHandler(void);
+
+#endif /* GD32F1X0_IT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Analog_watchdog/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Analog_watchdog/main.c

@@ -0,0 +1,127 @@
+/*!
+    \file  main.c
+    \brief ADC analog watchdog
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+
+#ifdef GD32F130_150
+#define BOARD_ADC_CHANNEL ADC_CHANNEL_11
+#define ADC_GPIO_PIN GPIO_PIN_1
+#elif defined GD32F170_190
+#define BOARD_ADC_CHANNEL ADC_CHANNEL_10
+#define ADC_GPIO_PIN GPIO_PIN_0
+#endif
+
+void rcu_config(void);
+void gpio_config(void);
+void nvic_config(void);
+void adc_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* system clocks configuration */
+    rcu_config();
+    /* GPIO configuration */
+    gpio_config();
+    /* NVIC configuration */
+    nvic_config();
+    /* ADC configuration */
+    adc_config();
+
+    while(1);
+}
+
+/*!
+    \brief      configure the different system clocks
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable GPIOC clock */
+    rcu_periph_clock_enable(RCU_GPIOC);
+    /* enable ADC clock */
+    rcu_periph_clock_enable(RCU_ADC);
+    /* config ADC clock */
+    rcu_adc_clock_config(RCU_ADCCK_APB2_DIV6);
+}
+/*!
+    \brief      configure the gpio peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* configure led GPIO */
+    gd_eval_led_init(LED2);
+    /* config the GPIO as analog mode */
+    gpio_mode_set(GPIOC,GPIO_MODE_ANALOG,GPIO_PUPD_NONE,ADC_GPIO_PIN);
+}
+
+/*!
+    \brief      configure interrupt priority
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void nvic_config(void)
+{
+    nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
+    nvic_irq_enable(ADC_CMP_IRQn, 0, 0);
+}
+
+/*!
+    \brief      configure the adc peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_config(void)
+{
+    /* ADC regular channel length config */
+    adc_channel_length_config(ADC_REGULAR_CHANNEL,1);
+    /* ADC regular channel config */
+    adc_regular_channel_config(0,BOARD_ADC_CHANNEL,ADC_SAMPLETIME_239POINT5);
+    /* ADC external trigger enable */
+    adc_external_trigger_config(ADC_REGULAR_CHANNEL,ENABLE);
+    /* ADC external trigger source config */
+    adc_external_trigger_source_config(ADC_REGULAR_CHANNEL,ADC_EXTTRIG_REGULAR_SWRCST);
+    /* ADC data alignment config */
+    adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
+    /* enable ADC interface */
+    adc_enable();
+    /* ADC calibration and reset calibration */
+    adc_calibration_enable();
+    /* ADC contineous function enable */
+    adc_special_function_config(ADC_CONTINUOUS_MODE,ENABLE);
+
+    /* ADC analog watchdog threshold config */
+    adc_watchdog_threshold_config(0x0400,0x0A00);
+    /* ADC analog watchdog single channel config */
+    adc_watchdog_single_channel_enable(BOARD_ADC_CHANNEL);
+    /* ADC interrupt config */
+    adc_interrupt_enable(ADC_INT_WDE);
+
+    /* ADC software trigger enable */
+    adc_software_trigger_enable(ADC_REGULAR_CHANNEL);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Analog_watchdog/readme.txt

@@ -0,0 +1,25 @@
+/*!
+    \file  readme.txt
+    \brief description of the ADC analog watchdog
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/ GD32190R-EVAL board, it shows how to
+use the ADC analog watchdog to guard continuously an ADC channel.The ADC is configured 
+in continuous mode, PC1(GD32150R-EVAL) or PC0(GD32190R-EVAL) is chosen as analog
+input pin.The ADC clock is configured to 12MHz(below 14MHz or 28MHz).
+
+  When the channel11(channel10) converted value is over the programmed analog 
+watchdog high threshold (value 0x0A00) or below the analog watchdog low threshold
+(value 0x0400),an AWE interrupt will occur,and LED2 will turn on.  
+
+  The analog input pin should configured to AN mode and the ADC clock should 
+below 14MHz for GD32150R(28MHz for GD32190R-EVAL).

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Oversample_shift/gd32f1x0_it.c

@@ -0,0 +1,120 @@
+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+#include "main.h"
+#include "systick.h"
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while(1){
+    }
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while(1){
+    }
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while(1){
+    }
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while(1){
+    }
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+    delay_decrement();
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Oversample_shift/gd32f1x0_it.h

@@ -0,0 +1,42 @@
+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* this function handles NMI exception */
+void NMI_Handler(void);
+/* this function handles HardFault exception */
+void HardFault_Handler(void);
+/* this function handles MemManage exception */
+void MemManage_Handler(void);
+/* this function handles BusFault exception */
+void BusFault_Handler(void);
+/* this function handles UsageFault exception */
+void UsageFault_Handler(void);
+/* this function handles SVC exception */
+void SVC_Handler(void);
+/* this function handles DebugMon exception */
+void DebugMon_Handler(void);
+/* this function handles PendSV exception */
+void PendSV_Handler(void);
+/* this function handles SysTick exception */
+void SysTick_Handler(void);
+
+#endif /* GD32F1X0_IT_H */
+
+

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Oversample_shift/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Oversample_shift/main.c

@@ -0,0 +1,145 @@
+/*!
+    \file  main.c
+    \brief ADC oversample and shift 
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include "systick.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+
+#define BOARD_ADC_CHANNEL          ADC_CHANNEL_10
+#define ADC_GPIO_PORT              GPIOC
+#define ADC_GPIO_PIN               GPIO_PIN_0
+
+uint16_t adc_value = 0;
+
+void rcu_config(void);
+void gpio_config(void);
+void nvic_config(void);
+void adc_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+
+int main(void)
+{
+    /* system clocks configuration */
+    rcu_config();
+    /* systick configuration */
+    systick_config();  
+    /* GPIO configuration */
+    gpio_config();
+    /* NVIC configuration */
+    nvic_config();
+    /* ADC configuration */
+    adc_config();
+    /* configures COM port */
+    gd_eval_com_init(EVAL_COM1); 
+  
+    adc_software_trigger_enable(ADC_REGULAR_CHANNEL);
+
+    while(1){
+        adc_flag_clear(ADC_FLAG_EOC);
+        while(SET != adc_flag_get(ADC_FLAG_EOC)){
+        }
+        
+        adc_value = ADC_RDATA;
+        printf("16 times sample, 4 bits shift: 0x%x\r\n", adc_value);
+        delay_1ms(1000);
+    }
+}
+
+/*!
+    \brief      configure the different system clocks
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable GPIOC clock */
+    rcu_periph_clock_enable(RCU_GPIOC);
+    /* enable ADC clock */
+    rcu_periph_clock_enable(RCU_ADC);
+    /* config ADC clock */
+    rcu_adc_clock_config(RCU_ADCCK_APB2_DIV6);
+}
+
+/*!
+    \brief      configure the GPIO peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* config the GPIO as analog mode */
+    gpio_mode_set(ADC_GPIO_PORT, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, ADC_GPIO_PIN);
+}
+
+/*!
+    \brief      configure interrupt priority
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void nvic_config(void)
+{
+    nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
+    nvic_irq_enable(ADC_CMP_IRQn, 0, 0);
+}
+
+/*!
+    \brief      configure the ADC peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_config(void)
+{
+    /* ADC contineous function enable */
+    adc_special_function_config(ADC_CONTINUOUS_MODE, ENABLE);  
+    /* ADC trigger config */
+    adc_external_trigger_source_config(ADC_REGULAR_CHANNEL, ADC_EXTTRIG_REGULAR_SWRCST); 
+    /* ADC data alignment config */
+    adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
+    /* ADC channel length config */
+    adc_channel_length_config(ADC_REGULAR_CHANNEL, 1);
+ 
+    /* ADC regular channel config */
+    adc_regular_channel_config(0, BOARD_ADC_CHANNEL, ADC_SAMPLETIME_55POINT5);
+    adc_external_trigger_config(ADC_REGULAR_CHANNEL, ENABLE);
+
+    /* 16 times sample, 4 bits shift */
+    adc_oversample_mode_config(ADC_OVERSAMPLING_ALL_CONVERT, ADC_OVERSAMPLING_SHIFT_4B, ADC_OVERSAMPLING_RATIO_MUL16);
+    adc_oversample_mode_enable();
+    
+    /* enable ADC interface */
+    adc_enable();
+    delay_1ms(1);
+    /* ADC calibration and reset calibration */
+    adc_calibration_enable();
+}
+
+/* retarget the C library printf function to the USART */
+int fputc(int ch, FILE *f)
+{
+    usart_data_transmit(EVAL_COM1, (uint8_t)ch);
+    while(RESET == usart_flag_get(EVAL_COM1, USART_FLAG_TBE));
+
+    return ch;
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Oversample_shift/readme.txt

@@ -0,0 +1,22 @@
+/*!
+    \file  readme.txt
+    \brief description of the ADC oversample shift example
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32190R-EVAL board, it shows how to use
+the function of oversample and shift. In this demo, 16 times ratio of
+oversample and 4 bits shift are configured. PC0(channel10) is chosen as
+analog input pin. The ADC conversion begins by software, the converted 
+data is printed by USART.
+
+  The analog input pin should configured to analog mode.
+  Jump the JP14, JP15 to USART.

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Oversample_shift/systick.c

@@ -0,0 +1,61 @@
+/*!
+    \file  systick.c
+    \brief the systick configuration file
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include "systick.h"
+
+static uint32_t delay;
+
+/*!
+    \brief      configure systick
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void systick_config(void)
+{
+    /* setup systick timer for 1000Hz interrupts */
+    if (SysTick_Config(SystemCoreClock / 1000)){
+        /* capture error */
+        while (1);
+    }
+    /* configure the systick handler priority */
+    NVIC_SetPriority(SysTick_IRQn, 0x00);
+}
+
+/*!
+    \brief      delay a time in milliseconds
+    \param[in]  count: count in milliseconds
+    \param[out] none
+    \retval     none
+*/
+void delay_1ms(uint32_t count)
+{
+    delay = count;
+
+    while(0 != delay);
+}
+
+/*!
+    \brief      delay decrement
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void delay_decrement(void)
+{
+    if (0 != delay){
+        delay--;
+    }
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Oversample_shift/systick.h

@@ -0,0 +1,27 @@
+/*!
+    \file  systick.h
+    \brief the header file of systick
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef SYS_TICK_H
+#define SYS_TICK_H
+
+#include <stdint.h>
+
+/* configure systick */
+void systick_config(void);
+/* delay a time in milliseconds */
+void delay_1ms(uint32_t count);
+/* delay decrement */
+void delay_decrement(void);
+
+#endif /* SYS_TICK_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Regular_channel_discontinuous_mode/gd32f1x0_it.c

@@ -0,0 +1,116 @@
+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+#include "systick.h"
+#include "gd32f1x0_eval.h"
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+    delay_decrement();
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Regular_channel_discontinuous_mode/gd32f1x0_it.h

@@ -0,0 +1,40 @@
+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* NMI handle function */
+void NMI_Handler(void);
+/* HardFault handle function */
+void HardFault_Handler(void);
+/* MemManage handle function */
+void MemManage_Handler(void);
+/* BusFault handle function */
+void BusFault_Handler(void);
+/* UsageFault handle function */
+void UsageFault_Handler(void);
+/* SVC handle function */
+void SVC_Handler(void);
+/* DebugMon handle function */
+void DebugMon_Handler(void);
+/* PendSV handle function */
+void PendSV_Handler(void);
+/* SysTick handle function */
+void SysTick_Handler(void);
+
+#endif /* GD32F1X0_IT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Regular_channel_discontinuous_mode/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Regular_channel_discontinuous_mode/main.c

@@ -0,0 +1,144 @@
+/*!
+    \file  main.c
+    \brief ADC discontinuous mode for regular channel
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "systick.h"
+#include "gd32f1x0_eval.h"
+
+uint16_t adc_value[16];
+
+void rcu_config(void);
+void gpio_config(void);
+void dma_config(void);
+void adc_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* system clocks configuration */
+    rcu_config();
+    /* GPIO configuration */
+    gpio_config();
+    /* SYSTICK configuration */
+    systick_config();
+    /* DMA configuration */
+    dma_config();
+    /* ADC configuration */
+    adc_config();
+
+    while(1){
+        delay_1ms(1000);
+        /* ADC software trigger enable */
+        adc_software_trigger_enable(ADC_REGULAR_CHANNEL);
+    }
+}
+
+/*!
+    \brief      configure the different system clocks
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable GPIOC clock */
+    rcu_periph_clock_enable(RCU_GPIOC);
+    /* enable ADC clock */
+    rcu_periph_clock_enable(RCU_ADC);
+    /* enable DMA clock */
+    rcu_periph_clock_enable(RCU_DMA);
+    /* config ADC clock */
+    rcu_adc_clock_config(RCU_ADCCK_APB2_DIV6);
+}
+/*!
+    \brief      configure the gpio peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* config the GPIO as analog mode */
+    gpio_mode_set(GPIOA,GPIO_MODE_ANALOG,GPIO_PUPD_NONE,GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
+    gpio_mode_set(GPIOA,GPIO_MODE_ANALOG,GPIO_PUPD_NONE,GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
+}
+
+/*!
+    \brief      configure the dma peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dma_config(void)
+{
+    /* ADC DMA_channel configuration */
+    dma_deinit(DMA_CH0);
+    dma_periph_address_config(DMA_CH0,(uint32_t)(&ADC_RDATA));
+    dma_memory_address_config(DMA_CH0,(uint32_t)(adc_value));
+    dma_transfer_direction_config(DMA_CH0,DMA_PERIPHERAL_TO_MEMORY);
+    dma_memory_width_config(DMA_CH0,DMA_MEMORY_WIDTH_16BIT);
+    dma_periph_width_config(DMA_CH0,DMA_PERIPHERAL_WIDTH_16BIT);
+    dma_priority_config(DMA_CH0,DMA_PRIORITY_HIGH);
+    dma_transfer_number_config(DMA_CH0,16);
+    dma_periph_increase_disable(DMA_CH0);
+    dma_memory_increase_enable(DMA_CH0);
+    dma_circulation_enable(DMA_CH0);
+    dma_channel_enable(DMA_CH0);
+}
+
+/*!
+    \brief      configure the adc peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_config(void)
+{
+    /* ADC channel length config */
+    adc_channel_length_config(ADC_REGULAR_CHANNEL,8);
+
+    /* ADC regular channel config */
+    adc_regular_channel_config(0,ADC_CHANNEL_0,ADC_SAMPLETIME_239POINT5);
+    adc_regular_channel_config(1,ADC_CHANNEL_1,ADC_SAMPLETIME_239POINT5);
+    adc_regular_channel_config(2,ADC_CHANNEL_2,ADC_SAMPLETIME_239POINT5);
+    adc_regular_channel_config(3,ADC_CHANNEL_3,ADC_SAMPLETIME_239POINT5);
+    adc_regular_channel_config(4,ADC_CHANNEL_4,ADC_SAMPLETIME_239POINT5);
+    adc_regular_channel_config(5,ADC_CHANNEL_5,ADC_SAMPLETIME_239POINT5);
+    adc_regular_channel_config(6,ADC_CHANNEL_6,ADC_SAMPLETIME_239POINT5);
+    adc_regular_channel_config(7,ADC_CHANNEL_7,ADC_SAMPLETIME_239POINT5);
+
+    /* ADC external trigger enable */
+    adc_external_trigger_config(ADC_REGULAR_CHANNEL,ENABLE);
+    /* ADC external trigger source config */
+    adc_external_trigger_source_config(ADC_REGULAR_CHANNEL,ADC_EXTTRIG_REGULAR_SWRCST);
+    /* ADC data alignment config */
+    adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
+    /* ADC discontinuous mode */
+    adc_discontinuous_mode_config(ADC_REGULAR_CHANNEL,3);
+    /* enable ADC interface */
+    adc_enable();
+    /* ADC calibration and reset calibration */
+    adc_calibration_enable();
+    /* ADC DMA function enable */
+    adc_dma_mode_enable();
+
+    /* ADC software trigger enable */
+    adc_software_trigger_enable(ADC_REGULAR_CHANNEL);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Regular_channel_discontinuous_mode/readme.txt

@@ -0,0 +1,21 @@
+/*!
+    \file  readme.txt
+    \brief description of the ADC discontinuous mode
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/ GD32190R-EVAL board, it shows how to
+use the ADC discontinuous mode.The ADC is configured in discontinuous mode, group length
+is 8,conversion length is 3, using software trigger. Every trigger convert 3 channels.
+The ADC clock is configured to 12MHz(below 14MHz or 28MHz).
+
+  You can use the watch window to see the conversion result.
+ 

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Regular_channel_discontinuous_mode/systick.c

@@ -0,0 +1,63 @@
+/*!
+    \file  systick.c
+    \brief the systick configuration file
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include "systick.h"
+
+volatile static uint32_t delay;
+
+/*!
+    \brief      configure systick
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void systick_config(void)
+{
+    /* setup systick timer for 1000Hz interrupts */
+    if (SysTick_Config(SystemCoreClock / 1000U)){
+        /* capture error */
+        while (1){
+        }
+    }
+    /* configure the systick handler priority */
+    NVIC_SetPriority(SysTick_IRQn, 0x00U);
+}
+
+/*!
+    \brief      delay a time in milliseconds
+    \param[in]  count: count in milliseconds
+    \param[out] none
+    \retval     none
+*/
+void delay_1ms(uint32_t count)
+{
+    delay = count;
+
+    while(0U != delay){
+    }
+}
+
+/*!
+    \brief      delay decrement
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void delay_decrement(void)
+{
+    if (0U != delay){
+        delay--;
+    }
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Regular_channel_discontinuous_mode/systick.h

@@ -0,0 +1,27 @@
+/*!
+    \file  systick.h
+    \brief the header file of systick
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef SYS_TICK_H
+#define SYS_TICK_H
+
+#include <stdint.h>
+
+/* configure systick */
+void systick_config(void);
+/* delay a time in milliseconds */
+void delay_1ms(uint32_t count);
+/* delay decrement */
+void delay_decrement(void);
+
+#endif /* SYS_TICK_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Regular_channel_with_DMA/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Regular_channel_with_DMA/main.c

@@ -0,0 +1,132 @@
+/*!
+    \file  main.c
+    \brief ADC_regular_channel_with_DMA
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+
+#ifdef GD32F130_150
+#define BOARD_ADC_CHANNEL ADC_CHANNEL_11
+#define ADC_GPIO_PIN GPIO_PIN_1
+#elif defined GD32F170_190
+#define BOARD_ADC_CHANNEL ADC_CHANNEL_10
+#define ADC_GPIO_PIN GPIO_PIN_0
+#endif /* GD32F130_150 */
+
+uint16_t adc_value;
+
+void rcu_config(void);
+void gpio_config(void);
+void dma_config(void);
+void adc_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* system clocks configuration */
+    rcu_config();
+    /* GPIO configuration */
+    gpio_config();
+    /* DMA configuration */
+    dma_config();
+    /* ADC configuration */
+    adc_config();
+
+    while(1);
+}
+
+/*!
+    \brief      configure the different system clocks
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable GPIOC clock */
+    rcu_periph_clock_enable(RCU_GPIOC);
+    /* enable DMA clock */
+    rcu_periph_clock_enable(RCU_DMA);
+    /* enable ADC clock */
+    rcu_periph_clock_enable(RCU_ADC);
+    /* config ADC clock */
+    rcu_adc_clock_config(RCU_ADCCK_APB2_DIV6);
+}
+/*!
+    \brief      configure the gpio peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    gpio_mode_set(GPIOC,GPIO_MODE_ANALOG,GPIO_PUPD_NONE,ADC_GPIO_PIN);
+}
+
+/*!
+    \brief      configure the dma peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dma_config(void)
+{
+    /* ADC_DMA_channel configuration */
+    dma_deinit(DMA_CH0);
+    dma_periph_address_config(DMA_CH0,(uint32_t)(&ADC_RDATA));
+    dma_memory_address_config(DMA_CH0,(uint32_t)(&adc_value));
+    dma_transfer_direction_config(DMA_CH0,DMA_PERIPHERAL_TO_MEMORY);
+    dma_memory_width_config(DMA_CH0,DMA_MEMORY_WIDTH_16BIT);
+    dma_periph_width_config(DMA_CH0,DMA_PERIPHERAL_WIDTH_16BIT);
+    dma_priority_config(DMA_CH0,DMA_PRIORITY_HIGH);
+    dma_transfer_number_config(DMA_CH0,1);
+    dma_periph_increase_disable(DMA_CH0);
+    dma_memory_increase_enable(DMA_CH0);
+    dma_circulation_enable(DMA_CH0);
+    dma_channel_enable(DMA_CH0);
+}
+
+/*!
+    \brief      configure the adc peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_config(void)
+{
+    /* ADC channel length config */
+    adc_channel_length_config(ADC_REGULAR_CHANNEL,1);
+    /* ADC regular channel config */
+    adc_regular_channel_config(0,BOARD_ADC_CHANNEL,ADC_SAMPLETIME_239POINT5);
+    /* ADC external trigger enable */
+    adc_external_trigger_config(ADC_REGULAR_CHANNEL,ENABLE);
+    /* ADC external trigger source config */
+    adc_external_trigger_source_config(ADC_REGULAR_CHANNEL,ADC_EXTTRIG_REGULAR_SWRCST);
+    /* ADC data alignment config */
+    adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
+    /* enable ADC interface */
+    adc_enable();
+    /* ADC calibration and reset calibration */
+    adc_calibration_enable();
+    /* ADC DMA function enable */
+    adc_dma_mode_enable();
+    /* ADC contineous function enable */
+    adc_special_function_config(ADC_CONTINUOUS_MODE,ENABLE);
+    /* ADC software trigger enable */
+    adc_software_trigger_enable(ADC_REGULAR_CHANNEL);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Regular_channel_with_DMA/readme.txt

@@ -0,0 +1,25 @@
+/*!
+    \file  readme.txt
+    \brief description of the ADC regular channel with dma
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to
+use the ADC to convert analog signal to digital data through DMA.The ADC is 
+configured in continuous mode, PC1(GD32150R-EVAL) or PC0(GD32190R-EVAL) is chosen
+as analog input pin. The ADC clock is configured to 12MHz(below 14MHz or 28MHz).
+  As the AD convertion begins by software,the converted data from ADC_RDATA register
+to SRAM begins continuously.Users can change the VR1 on the GD32150R-EVAL/GD32190R-EVAL
+board,measure TP1(GD32150R-EVAL) or TP2(GD32190R-EVAL) pad board,and check if 
+its value matches the converted data through the watch window.
+
+  The analog input pin should configured to AN mode and the ADC clock should 
+below 14MHz for GD32150R(28MHz for GD32190R-EVAL).

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Resolution/gd32f1x0_it.c

@@ -0,0 +1,119 @@
+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+#include "systick.h"
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while(1){
+    }
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while(1){
+    }
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while(1){
+    }
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while(1){
+    }
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+    delay_decrement();
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Resolution/gd32f1x0_it.h

@@ -0,0 +1,42 @@
+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* this function handles NMI exception */
+void NMI_Handler(void);
+/* this function handles HardFault exception */
+void HardFault_Handler(void);
+/* this function handles MemManage exception */
+void MemManage_Handler(void);
+/* this function handles BusFault exception */
+void BusFault_Handler(void);
+/* this function handles UsageFault exception */
+void UsageFault_Handler(void);
+/* this function handles SVC exception */
+void SVC_Handler(void);
+/* this function handles DebugMon exception */
+void DebugMon_Handler(void);
+/* this function handles PendSV exception */
+void PendSV_Handler(void);
+/* this function handles SysTick exception */
+void SysTick_Handler(void);
+
+#endif /* GD32F1X0_IT_H */
+
+

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Resolution/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Resolution/main.c

@@ -0,0 +1,144 @@
+/*!
+    \file  main.c
+    \brief ADC resolution demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include "systick.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+
+#define BOARD_ADC_CHANNEL          ADC_CHANNEL_10
+#define ADC_GPIO_PORT              GPIOC
+#define ADC_GPIO_PIN               GPIO_PIN_0
+
+uint16_t adc_value;
+
+void rcu_config(void);
+void gpio_config(void);
+void nvic_config(void);
+void adc_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* system clocks configuration */
+    rcu_config();
+    /* systick configuration */
+    systick_config();  
+    /* GPIO configuration */
+    gpio_config();
+    /* NVIC configuration */
+    nvic_config();
+    /* configures COM port */
+    gd_eval_com_init(EVAL_COM1); 
+    
+    /* ADC configuration */
+    adc_config();
+    adc_software_trigger_enable(ADC_REGULAR_CHANNEL);
+  
+    while(1){
+        adc_flag_clear(ADC_FLAG_EOC);
+        while(SET != adc_flag_get(ADC_FLAG_EOC)){
+        }
+
+        adc_value = ADC_RDATA;
+        printf("6B: 0x%x\r\n", adc_value);
+        delay_1ms(500);
+    }
+}
+
+/*!
+    \brief      configure the different system clocks
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable GPIOC clock */
+    rcu_periph_clock_enable(RCU_GPIOC);
+    /* enable ADC clock */
+    rcu_periph_clock_enable(RCU_ADC);
+    /* config ADC clock */
+    rcu_adc_clock_config(RCU_ADCCK_APB2_DIV6);
+}
+
+/*!
+    \brief      configure the GPIO peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* config the GPIO as analog mode */
+    gpio_mode_set(ADC_GPIO_PORT, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, ADC_GPIO_PIN);
+}
+
+/*!
+    \brief      configure interrupt priority
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void nvic_config(void)
+{
+    nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
+    nvic_irq_enable(ADC_CMP_IRQn, 0, 0);
+}
+
+/*!
+    \brief      configure the ADC peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_config(void)
+{
+    /* ADC contineous function enable */
+    adc_special_function_config(ADC_CONTINUOUS_MODE, ENABLE);
+    /* ADC trigger config */
+    adc_external_trigger_source_config(ADC_REGULAR_CHANNEL, ADC_EXTTRIG_REGULAR_SWRCST); 
+    /* ADC data alignment config */
+    adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
+    /* ADC channel length config */
+    adc_channel_length_config(ADC_REGULAR_CHANNEL, 1);
+ 
+    /* ADC regular channel config */
+    adc_regular_channel_config(0, BOARD_ADC_CHANNEL, ADC_SAMPLETIME_55POINT5);
+    adc_external_trigger_config(ADC_REGULAR_CHANNEL, ENABLE);
+
+    /* ADC resolusion 6B */
+    printf("\r\nresolusion 6B:\r\n");
+    adc_resolution_config(ADC_RESOLUTION_6B);
+    
+    /* enable ADC interface */
+    adc_enable();
+    delay_1ms(1);
+    /* ADC calibration and reset calibration */
+    adc_calibration_enable();
+}
+
+/* retarget the C library printf function to the USART */
+int fputc(int ch, FILE *f)
+{
+    usart_data_transmit(EVAL_COM1, (uint8_t)ch);
+    while(RESET == usart_flag_get(EVAL_COM1, USART_FLAG_TBE));
+
+    return ch;
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Resolution/readme.txt

@@ -0,0 +1,21 @@
+/*!
+    \file  readme.txt
+    \brief description of the ADC resolution demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32190R-EVAL board, it shows how to use 
+the function of programmble resolusion. In this demo, 6B resolusion 
+is configured. PC0(channel10) is chosen as analog input pin. The ADC 
+conversion begins by software, the converted data is printed by USART.
+
+  The analog input pin should configured to analog mode.
+  Jump the JP14, JP15 to USART.

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Resolution/systick.c

@@ -0,0 +1,61 @@
+/*!
+    \file  systick.c
+    \brief the systick configuration file
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include "systick.h"
+
+static uint32_t delay;
+
+/*!
+    \brief      configure systick
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void systick_config(void)
+{
+    /* setup systick timer for 1000Hz interrupts */
+    if (SysTick_Config(SystemCoreClock / 1000)){
+        /* capture error */
+        while (1);
+    }
+    /* configure the systick handler priority */
+    NVIC_SetPriority(SysTick_IRQn, 0x00);
+}
+
+/*!
+    \brief      delay a time in milliseconds
+    \param[in]  count: count in milliseconds
+    \param[out] none
+    \retval     none
+*/
+void delay_1ms(uint32_t count)
+{
+    delay = count;
+
+    while(0 != delay);
+}
+
+/*!
+    \brief      delay decrement
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void delay_decrement(void)
+{
+    if (0 != delay){
+        delay--;
+    }
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Resolution/systick.h

@@ -0,0 +1,27 @@
+/*!
+    \file  systick.h
+    \brief the header file of systick
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef SYS_TICK_H
+#define SYS_TICK_H
+
+#include <stdint.h>
+
+/* configure systick */
+void systick_config(void);
+/* delay a time in milliseconds */
+void delay_1ms(uint32_t count);
+/* delay decrement */
+void delay_decrement(void);
+
+#endif /* SYS_TICK_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Temperature_Vref_Vbat/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Temperature_Vref_Vbat/main.c

@@ -0,0 +1,98 @@
+/*!
+    \file  main.c
+    \brief ADC channel of temperature,Vref and Vbat
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+
+void rcu_config(void);
+void adc_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* system clocks configuration */
+    rcu_config();
+    /* ADC configuration */
+    adc_config();
+    /* USART configuration */
+    gd_eval_com_init(EVAL_COM1);
+
+    printf(" the temperature data is %d\r\n",adc_inserted_data_read(ADC_INSERTED_CHANNEL_0));
+    printf(" the reference voltage data is %d\r\n",adc_inserted_data_read(ADC_INSERTED_CHANNEL_1));
+    printf(" the battery voltage data is %d\r\n",adc_inserted_data_read(ADC_INSERTED_CHANNEL_2));
+    while(1);
+}
+
+/*!
+    \brief      configure the different system clocks
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable ADC clock */
+    rcu_periph_clock_enable(RCU_ADC);
+    /* config ADC clock */
+    rcu_adc_clock_config(RCU_ADCCK_APB2_DIV6);
+}
+
+/*!
+    \brief      configure the adc peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_config(void)
+{
+    /* ADC channel length config */
+    adc_channel_length_config(ADC_INSERTED_CHANNEL,3);
+
+    /* ADC regular channel config */
+    adc_inserted_channel_config(0,ADC_CHANNEL_16,ADC_SAMPLETIME_239POINT5);
+    adc_inserted_channel_config(1,ADC_CHANNEL_17,ADC_SAMPLETIME_239POINT5);
+    adc_inserted_channel_config(2,ADC_CHANNEL_18,ADC_SAMPLETIME_239POINT5);
+
+    /* ADC external trigger enable */
+    adc_external_trigger_config(ADC_INSERTED_CHANNEL,ENABLE);
+    /* ADC external trigger source config */
+    adc_external_trigger_source_config(ADC_INSERTED_CHANNEL,ADC_EXTTRIG_INSERTED_SWRCST);
+    /* ADC data alignment config */
+    adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
+    /* ADC SCAN function enable */
+    adc_special_function_config(ADC_SCAN_MODE,ENABLE);
+    /* ADC Vbat and temperature channel enable */
+    adc_tempsensor_vrefint_enable();
+    /* enable ADC interface */
+    adc_enable();
+    /* ADC calibration and reset calibration */
+    adc_calibration_enable();
+
+    /* ADC software trigger enable */
+    adc_software_trigger_enable(ADC_INSERTED_CHANNEL);
+}
+
+/* retarget the C library printf function to the USART */
+int fputc(int ch, FILE *f)
+{
+    usart_data_transmit(EVAL_COM1, (uint8_t)ch);
+    while(RESET == usart_flag_get(EVAL_COM1, USART_FLAG_TBE));
+    return ch;
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Temperature_Vref_Vbat/readme.txt

@@ -0,0 +1,24 @@
+/*!
+    \file  readme.txt
+    \brief description of the ADC TIMER trigger injected channel
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to 
+use the ADC to convert analog signal to digital data.The ADC is configured 
+in dependent mode, inner channel16(temperature sensor channel),channel17(VREF channel) 
+and channel18(VBAT/2 channel) are chosen as analog input pin. The ADC clock 
+is configured to 12MHz.
+  As the AD convertion begins by software,the converted data in the ADC_IDTRx register
+,where the x is 0 to 2.    
+ 
+  The analog input pin should configured to AN mode and the ADC clock should 
+below 14MHz for GD32150R(28MHz for GD32190R-EVAL).

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Timer_trigger_injected_channel/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Timer_trigger_injected_channel/main.c

@@ -0,0 +1,155 @@
+/*!
+    \file  main.c
+    \brief TIMER trigger injected channel of ADC
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+#include "systick.h"
+
+uint16_t adc_value[16];
+
+void rcu_config(void);
+void gpio_config(void);
+void nvic_config(void);
+void timer_config(void);
+void adc_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* system clocks configuration */
+    rcu_config();
+    /* GPIO configuration */
+    gpio_config();
+    /* NVIC configuration */
+    nvic_config();
+    /* TIMER configuration */
+    timer_config();
+    /* ADC configuration */
+    adc_config();
+
+    timer_enable(TIMER1);
+    while(1);
+}
+
+/*!
+    \brief      configure the different system clocks
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable GPIOC clock */
+    rcu_periph_clock_enable(RCU_GPIOC);
+    /* enable ADC clock */
+    rcu_periph_clock_enable(RCU_ADC);
+    /* enable timer1 clock */
+    rcu_periph_clock_enable(RCU_TIMER1);
+    /* config ADC clock */
+    rcu_adc_clock_config(RCU_ADCCK_APB2_DIV6);
+}
+/*!
+    \brief      configure the gpio peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* configures led GPIO */
+    gd_eval_led_init(LED2);
+
+    /* config the GPIO as analog mode */
+    gpio_mode_set(GPIOA,GPIO_MODE_ANALOG,GPIO_PUPD_NONE,GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
+}
+
+/*!
+    \brief      configure interrupt priority
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void nvic_config(void)
+{
+    nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
+    nvic_irq_enable(ADC_CMP_IRQn, 0, 0);
+}
+
+/*!
+    \brief      configure the timer peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void timer_config(void)
+{
+    timer_oc_parameter_struct timer_ocintpara;
+    timer_parameter_struct timer_initpara;
+
+    /* TIMER1 configuration */
+    timer_initpara.prescaler         = 7199;
+    timer_initpara.alignedmode       = TIMER_COUNTER_EDGE;
+    timer_initpara.counterdirection  = TIMER_COUNTER_UP;
+    timer_initpara.period            = 9999;
+    timer_initpara.clockdivision     = TIMER_CKDIV_DIV1;
+    timer_initpara.repetitioncounter = 0;
+    timer_init(TIMER1,&timer_initpara);
+
+    /* CH1,CH2 and CH3 configuration in PWM mode1 */
+    timer_ocintpara.ocpolarity  = TIMER_OC_POLARITY_HIGH;
+    timer_ocintpara.outputstate = TIMER_CCX_ENABLE;
+
+    timer_channel_output_config(TIMER1,TIMER_CH_0,&timer_ocintpara);
+
+    timer_channel_output_pulse_value_config(TIMER1,TIMER_CH_0,3999);
+    timer_channel_output_mode_config(TIMER1,TIMER_CH_0,TIMER_OC_MODE_PWM1);
+    timer_channel_output_shadow_config(TIMER1,TIMER_CH_0,TIMER_OC_SHADOW_DISABLE);
+}
+
+/*!
+    \brief      configure the adc peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_config(void)
+{
+    /* ADC channel length config */
+    adc_channel_length_config(ADC_INSERTED_CHANNEL,4);
+
+    /* ADC inserted channel config */
+    adc_inserted_channel_config(0,ADC_CHANNEL_0,ADC_SAMPLETIME_239POINT5);
+    adc_inserted_channel_config(1,ADC_CHANNEL_1,ADC_SAMPLETIME_239POINT5);
+    adc_inserted_channel_config(2,ADC_CHANNEL_2,ADC_SAMPLETIME_239POINT5);
+    adc_inserted_channel_config(3,ADC_CHANNEL_3,ADC_SAMPLETIME_239POINT5);
+
+    /* ADC external trigger enable */
+    adc_external_trigger_config(ADC_INSERTED_CHANNEL,ENABLE);
+    /* ADC external trigger source config */
+    adc_external_trigger_source_config(ADC_INSERTED_CHANNEL,ADC_EXTTRIG_INSERTED_T1_CH0);
+    /* ADC data alignment config */
+    adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
+    /* enable ADC interface */
+    adc_enable();
+    /* ADC calibration and reset calibration */
+    adc_calibration_enable();
+    /* ADC SCAN function enable */
+    adc_special_function_config(ADC_SCAN_MODE,ENABLE);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/ADC/Timer_trigger_injected_channel/readme.txt

@@ -0,0 +1,19 @@
+/*!
+    \file  readme.txt
+    \brief description of the ADC TIMER trigger injected channel
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/ GD32190R-EVAL board, it shows how to
+convert ADC inserted group channels continuously using TIM1 external trigger.The
+inserted group length is 4, the scan mode is set, every compare event will trigger
+ADC convert all the channels in the inserted group.The ADC clock is configured to 
+12MHz(below 14MHz or 28MHz).

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Dual_CAN_communication/gd32f1x0_it.c

@@ -0,0 +1,153 @@
+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+
+can_receive_message_struct receive_message;
+extern FlagStatus can0_receive_flag;
+extern FlagStatus can1_receive_flag;
+extern FlagStatus can0_error_flag;
+extern FlagStatus can1_error_flag;
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles CAN0 RX0 exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void CAN0_RX0_IRQHandler(void)
+{
+    /* check the receive message */
+    can_message_receive(CAN0, CAN_FIFO0, &receive_message);
+    
+    if((0x300>>1 == receive_message.rx_sfid)&&(CAN_FF_STANDARD == receive_message.rx_ff)&&(2 == receive_message.rx_dlen)){
+        can0_receive_flag = SET; 
+    }else{
+        can0_error_flag = SET; 
+    }
+}
+/*!
+    \brief      this function handles CAN1 RX0 exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void CAN1_RX0_IRQHandler(void)
+{
+    /* check the receive message */
+    can_message_receive(CAN1, CAN_FIFO0, &receive_message);
+    
+    if((0x300>>1 == receive_message.rx_sfid)&&(CAN_FF_STANDARD == receive_message.rx_ff)&&(2 == receive_message.rx_dlen)){
+        can1_receive_flag = SET; 
+    }else{
+        can1_error_flag = SET; 
+    }
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Dual_CAN_communication/gd32f1x0_it.h

@@ -0,0 +1,44 @@
+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* NMI handle function */
+void NMI_Handler(void);
+/* HardFault handle function */
+void HardFault_Handler(void);
+/* MemManage handle function */
+void MemManage_Handler(void);
+/* BusFault handle function */
+void BusFault_Handler(void);
+/* UsageFault handle function */
+void UsageFault_Handler(void);
+/* SVC handle function */
+void SVC_Handler(void);
+/* DebugMon handle function */
+void DebugMon_Handler(void);
+/* PendSV handle function */
+void PendSV_Handler(void);
+/* SysTick handle function */
+void SysTick_Handler(void);
+/* CAN0 RX0 handle function */
+void CAN0_RX0_IRQHandler(void);
+/* CAN1 RX0 handle function */
+void CAN1_RX0_IRQHandler(void);
+
+#endif /* GD32F1X0_IT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Dual_CAN_communication/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Dual_CAN_communication/main.c

@@ -0,0 +1,285 @@
+/*!
+    \file  main.c
+    \brief dual CAN communication in normal mode
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+
+/* select CAN baudrate */
+/* 1MBps */
+#define CAN_BAUDRATE  1000
+/* 500kBps */
+/* #define CAN_BAUDRATE  500 */
+/* 250kBps */
+/* #define CAN_BAUDRATE  250 */
+/* 125kBps */
+/* #define CAN_BAUDRATE  125 */
+/* 100kBps */ 
+/* #define CAN_BAUDRATE  100 */
+/* 50kBps */ 
+/* #define CAN_BAUDRATE  50 */
+/* 20kBps */ 
+/* #define CAN_BAUDRATE  20 */
+
+extern can_receive_message_struct receive_message;
+FlagStatus can0_receive_flag;
+FlagStatus can1_receive_flag;
+FlagStatus can0_error_flag;
+FlagStatus can1_error_flag;
+can_parameter_struct            can_init_parameter;
+can_filter_parameter_struct     can_filter_parameter;
+can_trasnmit_message_struct transmit_message;
+
+void nvic_config(void);
+void led_config(void);
+void can_gpio_config(void);
+void can_config(can_parameter_struct can_parameter, can_filter_parameter_struct can_filter);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    can0_receive_flag = RESET;
+    can1_receive_flag = RESET;
+    can0_error_flag = RESET;
+    can1_error_flag = RESET;
+    
+    /* configure GPIO */
+    can_gpio_config();
+    
+    /* configure NVIC */
+    nvic_config();
+    
+    /* configure USART */
+    gd_eval_com_init(EVAL_COM2);
+    
+    /* configure Wakeup key or Tamper key */
+    gd_eval_key_init(KEY_WAKEUP, KEY_MODE_GPIO);
+    gd_eval_key_init(KEY_TAMPER, KEY_MODE_GPIO);
+    
+    printf("\r\nGD32F1x0 dual CAN test, please press Wakeup key or Tamper key to start communication!\r\n");
+    /* configure leds */
+    led_config();
+    gd_eval_led_off(LED1);
+    gd_eval_led_off(LED2);
+    gd_eval_led_off(LED3);
+    gd_eval_led_off(LED4);
+    
+    /* initialize CAN and filter */
+    can_config(can_init_parameter, can_filter_parameter);
+    
+    /* enable phy */
+    can_phy_enable(CAN0);
+
+    /* enable can receive FIFO0 not empty interrupt */
+    can_interrupt_enable(CAN0, CAN_INTEN_RFNEIE0);
+    can_interrupt_enable(CAN1, CAN_INTEN_RFNEIE0);
+    
+    /* initialize transmit message */
+    transmit_message.tx_sfid = 0x300>>1;
+    transmit_message.tx_efid = 0x00;
+    transmit_message.tx_ft = CAN_FT_DATA;
+    transmit_message.tx_ff = CAN_FF_STANDARD;
+    transmit_message.tx_dlen = 2;
+
+    while(1){
+        /* test whether the Tamper key is pressed */
+        if(0 == gd_eval_key_state_get(KEY_TAMPER)){
+            transmit_message.tx_data[0] = 0x55;
+            transmit_message.tx_data[1] = 0xAA;
+            printf("\r\n can0 transmit data:%x,%x", transmit_message.tx_data[0],transmit_message.tx_data[1]);
+            /* transmit message */
+            can_message_transmit(CAN0, &transmit_message);
+            /* waiting for the Tamper key up */
+            while(0 == gd_eval_key_state_get(KEY_TAMPER));
+        }
+        /* test whether the Wakeup key is pressed */
+        if(0 == gd_eval_key_state_get(KEY_WAKEUP)){
+            transmit_message.tx_data[0] = 0xAA;
+            transmit_message.tx_data[1] = 0x55;
+            printf("\r\n can1 transmit data:%x,%x", transmit_message.tx_data[0],transmit_message.tx_data[1]);
+            /* transmit message */
+            can_message_transmit(CAN1, &transmit_message);
+            /* waiting for the Wakeup key up */
+            while(0 == gd_eval_key_state_get(KEY_WAKEUP));
+        }
+        /* CAN0 receive data correctly, the received data is printed */
+        if(SET == can0_receive_flag){
+            can0_receive_flag = RESET;
+            printf("\r\n can0 receive data:%x,%x",receive_message.rx_data[0],receive_message.rx_data[1]);
+            gd_eval_led_toggle(LED3);
+        }
+        /* CAN1 receive data correctly, the received data is printed */
+        if(SET == can1_receive_flag){
+            can1_receive_flag = RESET;
+            gd_eval_led_toggle(LED4);
+            printf("\r\n can1 receive data:%x,%x",receive_message.rx_data[0],receive_message.rx_data[1]);
+        }
+        /* CAN0 error */
+        if(SET == can0_error_flag){
+            can0_error_flag = RESET;
+            printf("\r\n can0 communication error");
+        }
+        /* CAN1 error */
+        if(SET == can1_error_flag){
+            can1_error_flag = RESET;
+            printf("\r\n can1 communication error");
+        }
+    }
+}
+
+/*!
+    \brief      initialize CAN and filter
+    \param[in]  can_parameter
+      \arg        can_parameter_struct
+    \param[in]  can_filter
+      \arg        can_filter_parameter_struct
+    \param[out] none
+    \retval     none
+*/
+void can_config(can_parameter_struct can_parameter, can_filter_parameter_struct can_filter)
+{
+    /* initialize CAN register */
+    can_deinit(CAN0);
+    can_deinit(CAN1);
+    
+    /* initialize CAN parameters */
+    can_parameter.time_triggered=DISABLE;
+    can_parameter.auto_bus_off_recovery=DISABLE;
+    can_parameter.auto_wake_up=DISABLE;
+    can_parameter.auto_retrans=DISABLE;
+    can_parameter.rec_fifo_overwrite=DISABLE;
+    can_parameter.trans_fifo_order=DISABLE;
+    can_parameter.working_mode=CAN_NORMAL_MODE;
+    can_parameter.resync_jump_width=CAN_BT_SJW_1TQ;
+    can_parameter.time_segment_1=CAN_BT_BS1_4TQ;
+    can_parameter.time_segment_2=CAN_BT_BS2_3TQ;
+    
+    /* 1MBps */
+#if CAN_BAUDRATE == 1000
+    can_parameter.prescaler =9;
+    /* 500KBps */
+#elif CAN_BAUDRATE == 500 
+    can_parameter.prescaler =18;
+    /* 250KBps */
+#elif CAN_BAUDRATE == 250 
+    can_parameter.prescaler =36;
+    /* 125KBps */
+#elif CAN_BAUDRATE == 125 
+    can_parameter.prescaler =72;
+    /* 100KBps */
+#elif  CAN_BAUDRATE == 100 
+    can_parameter.prescaler =90;
+    /* 50KBps */
+#elif  CAN_BAUDRATE == 50 
+    can_parameter.prescaler =180;
+    /* 20KBps */
+#elif  CAN_BAUDRATE == 20 
+    can_parameter.prescaler =450;
+#else
+    #error "please select list can baudrate in private defines in main.c "
+#endif  
+    /* initialize CAN */
+    can_init(CAN0, &can_parameter);
+    can_init(CAN1, &can_parameter);
+    
+    /* initialize filter */ 
+    can_filter.filter_number=0;
+    can_filter.filter_mode = CAN_FILTERMODE_MASK;
+    can_filter.filter_bits = CAN_FILTERBITS_32BIT;
+    can_filter.filter_list_high = 0x3000;
+    can_filter.filter_list_low = 0x0000;
+    can_filter.filter_mask_high = 0x3000;
+    can_filter.filter_mask_low = 0x0000;  
+    can_filter.filter_fifo_number = CAN_FIFO0;
+    can_filter.filter_enable=ENABLE;
+    
+    can_filter_init(&can_filter);
+    
+    /* CAN1 filter number */
+    can_filter.filter_number=15;
+    can_filter_init(&can_filter);
+}
+
+/*!
+    \brief      configure the nested vectored interrupt controller
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void nvic_config(void)
+{
+    /* configure CAN0 NVIC */
+    nvic_irq_enable(CAN0_RX0_IRQn,0,0);
+
+    /* configure CAN1 NVIC */
+    nvic_irq_enable(CAN1_RX0_IRQn,1,1);
+}
+
+/*!
+    \brief      configure the leds
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void led_config(void)
+{
+    gd_eval_led_init(LED1);
+    gd_eval_led_init(LED2);
+    gd_eval_led_init(LED3);
+    gd_eval_led_init(LED4);
+}
+
+/*!
+    \brief      configure GPIO
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void can_gpio_config(void)
+{
+    /* enable CAN clock */
+    rcu_periph_clock_enable(RCU_CAN0);
+    rcu_periph_clock_enable(RCU_CAN1);
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_GPIOB);
+    
+    /* configure CAN0 GPIO */
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_5);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_5);
+
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_6);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_6);
+    
+    /* configure CAN1 GPIO */
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_12);
+    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12);
+    gpio_af_set(GPIOB, GPIO_AF_9, GPIO_PIN_12);
+    
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_13);
+    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13);
+    gpio_af_set(GPIOB, GPIO_AF_9, GPIO_PIN_13);
+}
+
+/* retarget the C library printf function to the usart */
+int fputc(int ch, FILE *f)
+{
+    usart_data_transmit(EVAL_COM2, (uint8_t)ch);
+    while (RESET == usart_flag_get(EVAL_COM2, USART_FLAG_TBE));
+    return ch;
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Dual_CAN_communication/readme.txt

@@ -0,0 +1,33 @@
+/*!
+    \file  readme.txt
+    \brief description of the dual can communication demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32190R-EVAL board, it shows how to configure the 
+CAN0 and CAN1 peripherals to send and receive CAN frames in normal mode. Pressing 
+Wakeup button or Tamper button:
+
+  When Tamper button is pressed, CAN0 sends a message to CAN1 and print it.
+when CAN1 receives correctly this message,the receive data will be printed
+and LED4 toggles a time. 
+
+  When Wakeup button is pressed, CAN1 sends a message to CAN0 and print it.
+when CAN0 receives correctly this message,the receive data will be printed
+and LED3 toggles a time.     
+
+  User can select one from the preconfigured CAN baud rates from the private 
+defines in main.c.These baudrates is correct only when the system clock frequency 
+is 72M.
+
+  Connect JP8 to CAN1
+  Connect JP4 CAN_L to JP3 CAN_L
+  Connect JP4 CAN_H to JP3 CAN_H

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Loopback_communication/gd32f1x0_it.c

@@ -0,0 +1,171 @@
+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+
+extern ErrStatus test_flag_interrupt;
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles CAN0 RX0 exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void CAN0_RX0_IRQHandler(void)
+{
+    can_receive_message_struct receive_message;
+    /* initialize receive message */
+    receive_message.rx_sfid=0x00;
+    receive_message.rx_efid=0x00;
+    receive_message.rx_ff=0;
+    receive_message.rx_dlen=0;
+    receive_message.rx_fi=0;
+    receive_message.rx_data[0]=0x00;
+    receive_message.rx_data[1]=0x00;
+    
+    /* check the receive message */
+    can_message_receive(CAN0, CAN_FIFO0, &receive_message);
+    
+    if((0x1234 == receive_message.rx_efid) && (CAN_FF_EXTENDED == receive_message.rx_ff)
+        && (2 == receive_message.rx_dlen) && (0xCADE == (receive_message.rx_data[1]<<8|receive_message.rx_data[0]))){
+        test_flag_interrupt = SUCCESS; 
+    }else{
+        test_flag_interrupt = ERROR; 
+    }
+}
+/*!
+    \brief      this function handles CAN1 RX0 exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void CAN1_RX0_IRQHandler(void)
+{
+    can_receive_message_struct receive_message;
+    /* initialize receive message */
+    receive_message.rx_sfid=0x00;
+    receive_message.rx_efid=0x00;
+    receive_message.rx_ff=0;
+    receive_message.rx_dlen=0;
+    receive_message.rx_fi=0;
+    receive_message.rx_data[0]=0x00;
+    receive_message.rx_data[1]=0x00;
+
+    /* check the receive message */
+    can_message_receive(CAN1, CAN_FIFO0, &receive_message);
+
+    if((0x1234 == receive_message.rx_efid) && (CAN_FF_EXTENDED == receive_message.rx_ff)
+        && (2 == receive_message.rx_dlen) && (0xCADE == (receive_message.rx_data[1]<<8|receive_message.rx_data[0]))){
+        test_flag_interrupt = SUCCESS; 
+    }else{
+        test_flag_interrupt = ERROR; 
+    }
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Loopback_communication/gd32f1x0_it.h

@@ -0,0 +1,44 @@
+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* NMI handle function */
+void NMI_Handler(void);
+/* HardFault handle function */
+void HardFault_Handler(void);
+/* MemManage handle function */
+void MemManage_Handler(void);
+/* BusFault handle function */
+void BusFault_Handler(void);
+/* UsageFault handle function */
+void UsageFault_Handler(void);
+/* SVC handle function */
+void SVC_Handler(void);
+/* DebugMon handle function */
+void DebugMon_Handler(void);
+/* PendSV handle function */
+void PendSV_Handler(void);
+/* SysTick handle function */
+void SysTick_Handler(void);
+/* CAN0 RX0 handle function */
+void CAN0_RX0_IRQHandler(void);
+/* CAN1 RX0 handle function */
+void CAN1_RX0_IRQHandler(void);
+
+#endif /* GD32F1X0_IT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Loopback_communication/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Loopback_communication/main.c

@@ -0,0 +1,264 @@
+/*!
+    \file  main.c
+    \brief CAN loopback communication in normal mode
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+
+/* select CAN */
+#define CAN0_USED
+//#define CAN1_USED
+
+#ifdef  CAN0_USED
+    #define CANX CAN0
+#else 
+    #define CANX CAN1
+#endif
+    
+volatile ErrStatus test_flag;
+ErrStatus test_flag_interrupt;
+
+void nvic_config(void);
+void led_config(void);
+ErrStatus can_loopback(void);
+ErrStatus can_loopback_interrupt(void);
+void can_loopback_init(can_parameter_struct can_parameter, can_filter_parameter_struct can_filter);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* enable CAN clock */
+    rcu_periph_clock_enable(RCU_CAN0);
+    rcu_periph_clock_enable(RCU_CAN1);
+    
+    /* configure NVIC */
+    nvic_config();
+    
+    /* configure leds */
+    led_config();
+    /* set all the leds off */
+    gd_eval_led_off(LED1);
+    gd_eval_led_off(LED2);
+    gd_eval_led_off(LED3);
+    gd_eval_led_off(LED4);
+    /* loopback of polling */
+    test_flag = can_loopback();
+ 
+    if(SUCCESS == test_flag){
+        /* loopback test is success */
+        gd_eval_led_on(LED1);
+        gd_eval_led_on(LED2);
+    }else{
+        /* loopback test is failed */
+        gd_eval_led_off(LED1);
+        gd_eval_led_off(LED2);
+    }
+    /* loopback of interrupt */
+    test_flag_interrupt = can_loopback_interrupt();
+
+    if(SUCCESS == test_flag_interrupt){
+        /* interrupt loopback test is success */
+        gd_eval_led_on(LED3);
+        gd_eval_led_on(LED4);
+    }else{
+        /* interrupt loopback test is failed */
+        gd_eval_led_off(LED3);
+        gd_eval_led_off(LED4);
+    }
+    while (1);
+}
+
+/*!
+    \brief      function for CAN loopback communication
+    \param[in]  none
+    \param[out] none
+    \retval     ErrStatus
+*/
+ErrStatus can_loopback(void)
+{
+    can_parameter_struct            can_init_parameter;
+    can_filter_parameter_struct     can_filter_parameter;
+    can_trasnmit_message_struct     transmit_message;
+    can_receive_message_struct      receive_message;
+    uint32_t timeout = 0xFFFF;
+    uint8_t transmit_mailbox = 0;
+    /* initialize CAN */
+    can_loopback_init(can_init_parameter, can_filter_parameter);
+
+    /* initialize transmit message */
+    transmit_message.tx_sfid = 0x11;
+    transmit_message.tx_ft = CAN_FT_DATA;
+    transmit_message.tx_ff = CAN_FF_STANDARD;
+    transmit_message.tx_dlen = 2;
+    transmit_message.tx_data[0] = 0xAB;
+    transmit_message.tx_data[1] = 0xCD;
+    
+    /* transmit message */
+    transmit_mailbox = can_message_transmit(CANX, &transmit_message);
+    /* waiting for transmit completed */
+    while((can_transmit_states(CANX, transmit_mailbox) != CAN_TRANSMIT_OK) && (timeout != 0)){
+        timeout--;
+    }
+    timeout = 0xFFFF;
+    /* waiting for receive completed */
+    while((can_receive_message_length_get(CANX, CAN_FIFO0) < 1) && (timeout != 0)){
+        timeout--; 
+    }
+
+    /* initialize receive message*/
+    receive_message.rx_sfid=0x00;
+    receive_message.rx_ff=0;
+    receive_message.rx_dlen=0;
+    receive_message.rx_data[0]=0x00;
+    receive_message.rx_data[1]=0x00;
+    can_message_receive(CANX, CAN_FIFO0, &receive_message);
+    
+    /* check the receive message */
+    if((receive_message.rx_sfid==0x11) && (receive_message.rx_ff==CAN_FF_STANDARD)
+       && (receive_message.rx_dlen==2) && ((receive_message.rx_data[1]<<8|receive_message.rx_data[0])==0xCDAB)){
+        return SUCCESS;
+    }else{
+        return ERROR;
+    }
+}
+
+/*!
+    \brief      function for CAN loopback interrupt communication
+    \param[in]  none
+    \param[out] none
+    \retval     ErrStatus
+*/
+ErrStatus can_loopback_interrupt(void)
+{
+    can_parameter_struct         can_init_parameter;
+    can_filter_parameter_struct  can_filter_parameter;
+    can_trasnmit_message_struct transmit_message;
+    uint32_t timeout = 0x0000FFFF;
+    
+    /* initialize CAN and filter */
+    can_loopback_init(can_init_parameter, can_filter_parameter);
+
+    /* enable CAN receive FIFO0 not empty interrupt  */ 
+    can_interrupt_enable(CANX, CAN_INTEN_RFNEIE0);
+
+    /* initialize transmit message */
+    transmit_message.tx_sfid=0;
+    transmit_message.tx_efid=0x1234;
+    transmit_message.tx_ff=CAN_FF_EXTENDED;
+    transmit_message.tx_ft=CAN_FT_DATA;
+    transmit_message.tx_dlen=2;
+    transmit_message.tx_data[0]=0xDE;
+    transmit_message.tx_data[1]=0xCA;
+    /* transmit a message */
+    can_message_transmit(CANX, &transmit_message);
+    
+    /* waiting for receive completed */
+    while((test_flag_interrupt != SUCCESS) && (timeout != 0)){
+        timeout--;
+    }
+    if(0 == timeout){
+        test_flag_interrupt = ERROR;
+    }
+
+    /* disable CAN receive FIFO0 not empty interrupt  */ 
+    can_interrupt_disable(CANX, CAN_INTEN_RFNEIE0);
+    
+    return test_flag_interrupt;
+}
+
+/*!
+    \brief      initialize CAN and filter
+    \param[in]  can_parameter
+      \arg        can_parameter_struct
+    \param[in]  can_filter
+      \arg        can_filter_parameter_struct
+    \param[out] none
+    \retval     none
+*/
+void can_loopback_init(can_parameter_struct can_parameter, can_filter_parameter_struct can_filter)
+{
+    /* initialize CAN register */
+    can_deinit(CANX);
+    
+    /* initialize CAN */
+    can_parameter.time_triggered=DISABLE;
+    can_parameter.auto_bus_off_recovery=DISABLE;
+    can_parameter.auto_wake_up=DISABLE;
+    can_parameter.auto_retrans=DISABLE;
+    can_parameter.rec_fifo_overwrite=DISABLE;
+    can_parameter.trans_fifo_order=DISABLE;
+    can_parameter.working_mode=CAN_LOOPBACK_MODE;
+    /* configure baudrate to 125kbps */
+    can_parameter.resync_jump_width=CAN_BT_SJW_1TQ;
+    can_parameter.time_segment_1=CAN_BT_BS1_3TQ;
+    can_parameter.time_segment_2=CAN_BT_BS2_2TQ;
+    can_parameter.prescaler=96;
+    can_init(CANX, &can_parameter);
+
+    /* initialize filter */
+#ifdef  CAN0_USED
+    /* CAN0 filter number */
+    can_filter.filter_number=0;
+#else
+    /* CAN1 filter number */
+    can_filter.filter_number=15;
+#endif
+    /* initialize filter */    
+    can_filter.filter_mode = CAN_FILTERMODE_MASK;
+    can_filter.filter_bits = CAN_FILTERBITS_32BIT;
+    can_filter.filter_list_high = 0x0000;
+    can_filter.filter_list_low = 0x0000;
+    can_filter.filter_mask_high = 0x0000;
+    can_filter.filter_mask_low = 0x0000;  
+    can_filter.filter_fifo_number = CAN_FIFO0;
+    can_filter.filter_enable=ENABLE;
+    can_filter_init(&can_filter);
+}
+
+/*!
+    \brief      configure the nested vectored interrupt controller
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void nvic_config(void)
+{
+#ifdef  CAN0_USED
+    /* configure CAN0 NVIC */
+    nvic_irq_enable(CAN0_RX0_IRQn,0,0);
+#else
+    /* configure CAN1 NVIC */
+    nvic_irq_enable(CAN1_RX0_IRQn,0,0);
+#endif
+
+}
+
+/*!
+    \brief      configure the leds
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void led_config(void)
+{
+    gd_eval_led_init(LED1);
+    gd_eval_led_init(LED2);
+    gd_eval_led_init(LED3);
+    gd_eval_led_init(LED4);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Loopback_communication/readme.txt

@@ -0,0 +1,24 @@
+/*!
+    \file  readme.txt
+    \brief description of the can loopback communication demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32190R-EVAL board, it shows how to set a communication 
+with the CAN in loopback mode.
+
+  The example first performs a transmission and a reception of a standard data frame by 
+polling at 125 Kbps.If the received frame is successful, the LED1 and LED2 are on. 
+otherwise,the LED1 and LED2 are off. Then, an extended data frame is transmitted at 125 Kbps. 
+Reception is done in the interrupt handler when the message becomes pending in the FIFO0. If 
+the received frame is successful, the LED3 and LED4 are on. otherwise,the LED3 and LED4 are off.
+    
+  User can select CAN0 or CAN1 cell using the private defines in main.c.

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Network_communication/gd32f1x0_it.c

@@ -0,0 +1,144 @@
+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+
+FlagStatus receive_flag;
+can_receive_message_struct receive_message;
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles CAN0 RX0 exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void CAN0_RX0_IRQHandler(void)
+{
+    /* check the receive message */
+    can_message_receive(CAN0, CAN_FIFO0, &receive_message);
+    if((0x321 == receive_message.rx_sfid)&&(CAN_FF_STANDARD == receive_message.rx_ff) && (1 == receive_message.rx_dlen)){
+        receive_flag = SET;
+    }
+}
+/*!
+    \brief      this function handles CAN1 RX0 exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void CAN1_RX0_IRQHandler(void)
+{
+    /* check the receive message */
+    can_message_receive(CAN1, CAN_FIFO0, &receive_message);
+    if((0x321 == receive_message.rx_sfid)&&(CAN_FF_STANDARD == receive_message.rx_ff) && (1 == receive_message.rx_dlen)){
+        receive_flag = SET;
+    }
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Network_communication/gd32f1x0_it.h

@@ -0,0 +1,46 @@
+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* NMI handle function */
+void NMI_Handler(void);
+/* HardFault handle function */
+void HardFault_Handler(void);
+/* MemManage handle function */
+void MemManage_Handler(void);
+/* BusFault handle function */
+void BusFault_Handler(void);
+/* UsageFault handle function */
+void UsageFault_Handler(void);
+/* SVC handle function */
+void SVC_Handler(void);
+/* DebugMon handle function */
+void DebugMon_Handler(void);
+/* PendSV handle function */
+void PendSV_Handler(void);
+/* SysTick handle function */
+void SysTick_Handler(void);
+/* CAN0 RX0 handle function */
+void CAN0_RX0_IRQHandler(void);
+/* CAN1 RX0 handle function */
+void CAN1_RX0_IRQHandler(void);
+
+#endif /* GD32F1X0_IT_H */
+
+

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Network_communication/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Network_communication/main.c

@@ -0,0 +1,241 @@
+/*!
+    \file  main.c
+    \brief CAN networking communication in normal mode
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+
+/* select can */
+//#define CAN0_USED
+#define CAN1_USED
+
+#ifdef  CAN0_USED
+    #define CANX CAN0
+#else 
+    #define CANX CAN1
+#endif
+    
+extern FlagStatus receive_flag;
+uint8_t transmit_number = 0x0;
+extern can_receive_message_struct receive_message;
+can_trasnmit_message_struct transmit_message;
+    
+void nvic_config(void);
+void led_config(void);
+void gpio_config(void);
+ErrStatus can_networking(void);
+void can_networking_init(can_parameter_struct can_parameter, can_filter_parameter_struct can_filter);
+void delay(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    can_parameter_struct            can_init_parameter;
+    can_filter_parameter_struct     can_filter_parameter;
+
+    receive_flag = RESET;
+    /* configure Tamper key */
+    gd_eval_key_init(KEY_TAMPER, KEY_MODE_GPIO);
+    /* configure GPIO */
+    gpio_config();
+    /* configure USART */
+    gd_eval_com_init(EVAL_COM2);
+    /* configure NVIC */
+    nvic_config();
+    /* configure leds */
+    led_config();
+    /* set all leds off */
+    gd_eval_led_off(LED1);
+    gd_eval_led_off(LED2);
+    gd_eval_led_off(LED3);
+    gd_eval_led_off(LED4);
+    /* initialize CAN */
+    can_networking_init(can_init_parameter, can_filter_parameter);
+    /* enable phy */
+#ifdef CAN0_USED 
+    can_phy_enable(CANX);
+#endif
+    /* enable CAN receive FIFO0 not empty interrupt */
+    can_interrupt_enable(CANX, CAN_INTEN_RFNEIE0);
+    
+    /* initialize transmit message */
+    transmit_message.tx_sfid = 0x321;
+    transmit_message.tx_efid = 0x01;
+    transmit_message.tx_ft = CAN_FT_DATA;
+    transmit_message.tx_ff = CAN_FF_STANDARD;
+    transmit_message.tx_dlen = 1;
+    printf("please press the Tamper key to transmit data!\r\n");
+    while(1){
+        /* waiting for the Tamper key pressed */
+        while(0 == gd_eval_key_state_get(KEY_TAMPER)){
+            /* if transmit_number is 0x10, set it to 0x00 */
+            if(transmit_number == 0x10){
+                transmit_number = 0x00;
+            }else{
+                transmit_message.tx_data[0] = transmit_number++;
+                printf("transmit data: %x\r\n", transmit_message.tx_data[0]);
+                /* transmit message */
+                can_message_transmit(CANX, &transmit_message);
+                delay();
+                /* waiting for Tamper key up */
+                while(0 == gd_eval_key_state_get(KEY_TAMPER));
+            }
+        }
+        if(SET == receive_flag){
+            gd_eval_led_toggle(LED1);
+            receive_flag = RESET;
+            printf("recive data: %x\r\n", receive_message.rx_data[0]);
+        }
+    } 
+}
+
+/*!
+    \brief      initialize CAN and filter
+    \param[in]  can_parameter
+      \arg        can_parameter_struct
+    \param[in]  can_filter
+      \arg        can_filter_parameter_struct
+    \param[out] none
+    \retval     none
+*/
+void can_networking_init(can_parameter_struct can_parameter, can_filter_parameter_struct can_filter)
+{
+    /* initialize CAN register */
+    can_deinit(CANX);
+    
+    /* initialize CAN */
+    can_parameter.time_triggered=DISABLE;
+    can_parameter.auto_bus_off_recovery=DISABLE;
+    can_parameter.auto_wake_up=DISABLE;
+    can_parameter.auto_retrans=DISABLE;
+    can_parameter.rec_fifo_overwrite=DISABLE;
+    can_parameter.trans_fifo_order=DISABLE;
+    can_parameter.working_mode=CAN_NORMAL_MODE;
+    can_parameter.resync_jump_width=CAN_BT_SJW_1TQ;
+    can_parameter.time_segment_1=CAN_BT_BS1_3TQ;
+    can_parameter.time_segment_2=CAN_BT_BS2_2TQ;
+    /* baudrate 1Mbps */
+    can_parameter.prescaler=12;
+    can_init(CANX, &can_parameter);
+
+    /* initialize filter */
+#ifdef  CAN0_USED
+    /* CAN0 filter number */
+    can_filter.filter_number=0;
+#else
+    /* CAN1 filter number */
+    can_filter.filter_number=15;
+#endif
+    /* initialize filter */    
+    can_filter.filter_mode = CAN_FILTERMODE_MASK;
+    can_filter.filter_bits = CAN_FILTERBITS_32BIT;
+    can_filter.filter_list_high = 0x0000;
+    can_filter.filter_list_low = 0x0000;
+    can_filter.filter_mask_high = 0x0000;
+    can_filter.filter_mask_low = 0x0000;  
+    can_filter.filter_fifo_number = CAN_FIFO0;
+    can_filter.filter_enable=ENABLE;
+    can_filter_init(&can_filter);
+}
+
+/*!
+    \brief      configure the nested vectored interrupt controller
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void nvic_config(void)
+{
+#ifdef  CAN0_USED
+    /* configure CAN0 NVIC */
+    nvic_irq_enable(CAN0_RX0_IRQn,0,0);
+#else
+    /* configure CAN1 NVIC */
+    nvic_irq_enable(CAN1_RX0_IRQn,0,0);
+#endif
+
+}
+
+/*!
+    \brief      delay
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void delay(void)
+{
+    uint16_t nTime = 0x0000;
+
+    for(nTime = 0; nTime < 0xFFFF; nTime++){
+    }
+}
+
+/*!
+    \brief      configure the leds
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void led_config(void)
+{
+    gd_eval_led_init(LED1);
+    gd_eval_led_init(LED2);
+    gd_eval_led_init(LED3);
+    gd_eval_led_init(LED4);
+}
+
+/*!
+    \brief      configure GPIO
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* enable can clock */
+    rcu_periph_clock_enable(RCU_CAN0);
+    rcu_periph_clock_enable(RCU_CAN1);
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_GPIOB);
+    
+    /* configure CAN0 GPIO */
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_5);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_5);
+
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_6);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_6);
+    
+    /* configure CAN1 GPIO */
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_12);
+    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12);
+    gpio_af_set(GPIOB, GPIO_AF_9, GPIO_PIN_12);
+    
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_13);
+    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13);
+    gpio_af_set(GPIOB, GPIO_AF_9, GPIO_PIN_13);
+    
+}
+
+/* retarget the C library printf function to the usart */
+int fputc(int ch, FILE *f)
+{
+    usart_data_transmit(EVAL_COM2, (uint8_t)ch);
+    while (RESET == usart_flag_get(EVAL_COM2, USART_FLAG_TBE));
+    return ch;
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CAN/Network_communication/readme.txt

@@ -0,0 +1,27 @@
+/*!
+    \file  readme.txt
+    \brief description of the can network communication demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+    This demo is based on the GD32190R-EVAL board, it shows how to configure the CAN 
+  peripheral to send and receive CAN frames in normal mode.The frames are sent and print
+  transmit data by pressing Tamper Key push button. When the frames are received, the receive
+  data will be printed and the LED1 will toggle.
+ 
+    Connect JP8 to CAN1
+    This example is tested with at least two GD32190R-EVAL boards. The same program example is 
+  loaded in all boards and connect CAN_L and CAN_H pin of CAN0 or CAN1 to bus for sending 
+  and receiving frames.
+
+  User can select CAN0 or CAN1 cell using the private defines in main.c.
+
+

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CEC/Intercommunication/gd32f1x0_it.c

@@ -0,0 +1,237 @@
+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+#include "gd32f1x0_eval.h"
+#include "systick.h"
+
+/* array1 transmission */
+uint8_t senddata1[2] = {0xA5,0x5A};
+/* array2 transmission */
+uint8_t senddata2[2] = {0x5A,0xA5};
+/* receive array buffer  */
+uint8_t rcvdata[10];
+/* sent data pointer */
+uint8_t *transdata;
+__IO uint8_t rcvstatus = 0U;
+__IO uint8_t send_inc = 0U, rcv_inc = 0U;
+uint16_t senderrorcode = 0U;
+uint16_t rcverrorcode = 0U;
+__IO uint8_t bytenum = 0U;
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+        delay_decrement();
+}
+
+/*!
+    \brief      this function handles EXTI0_1 interrupt request
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+#ifdef GD32F170_190
+void EXTI0_1_IRQHandler(void)
+{
+    if(RESET != exti_flag_get(WAKEUP_KEY_EXTI_LINE)){
+        /* Tamper key press */
+        bytenum = 2U;
+        /* send CEC address */
+        cec_data_send(0x12U);
+        /* start transmission */
+        transdata = senddata1;
+        /* start transmission */
+        cec_transmission_start();
+        exti_flag_clear(WAKEUP_KEY_EXTI_LINE);
+    }
+}
+#endif /* GD32F170_190 */
+
+/*!
+    \brief      this function handles EXTI4_15 interrupt request
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void EXTI4_15_IRQHandler(void)
+{
+#ifdef GD32F130_150
+    if(RESET != exti_flag_get(USER_KEY_EXTI_LINE)){
+        /* Tamper key press */
+        bytenum = 2U;
+        /* send CEC address */
+        cec_data_send(0x12U);
+        transdata = senddata1;
+        /* start transmission */
+        cec_transmission_start();
+        exti_flag_clear(USER_KEY_EXTI_LINE);
+    }
+#endif /* GD32F130_150 */
+    
+    if(RESET != exti_flag_get(TAMPER_KEY_EXTI_LINE)){
+        /* Tamper key press */
+        bytenum = 2U;
+        /* send CEC address */
+        cec_data_send(0x12U);
+        /* start transmission */
+        transdata = senddata2;
+        /* start transmission */
+        cec_transmission_start();
+        exti_flag_clear(TAMPER_KEY_EXTI_LINE);
+    }
+}
+
+/*!
+    \brief      this function handles CEC interrupt request
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void CEC_IRQHandler(void)
+{
+    /* check if a reception error occured */
+    if(cec_interrupt_flag_get(CEC_INTF_RO | CEC_INTF_BRE | CEC_INTF_BPSE | CEC_INTF_BPLE | CEC_INTF_RAE)){
+        rcverrorcode = CEC_INTF;
+        cec_interrupt_flag_clear(CEC_INTF_RO | CEC_INTF_BRE | CEC_INTF_BPSE | CEC_INTF_BPLE | CEC_INTF_RAE);
+        rcvstatus  = 2U;
+    }
+    /* receive data */
+    if(cec_interrupt_flag_get(CEC_INTF_BR)){
+        rcvdata[rcv_inc] = cec_data_receive();
+        rcv_inc++;
+        cec_interrupt_flag_clear(CEC_INTF_BR);
+    }
+    /* check if the byte received is the last one of the message */
+    if(cec_interrupt_flag_get(CEC_INTF_REND)){
+        rcvstatus = 1U;
+        rcv_inc = 0U;
+        cec_interrupt_flag_clear(CEC_INTF_REND);
+    }
+
+    /* check if a transmission error occurred */
+    if(cec_interrupt_flag_get(CEC_INTF_ARBF | CEC_INTF_TU | CEC_INTF_TERR | CEC_INTF_TAERR)){
+        senderrorcode = CEC_INTF;
+        cec_interrupt_flag_clear(CEC_INTF_ARBF | CEC_INTF_TU | CEC_INTF_TERR | CEC_INTF_TAERR);
+    }
+  
+    /* check if end of message bit is set in the data to be transmitted */
+    if(cec_interrupt_flag_get(CEC_INTF_TEND)){
+        cec_interrupt_flag_clear(CEC_INTF_TEND| CEC_INTF_TBR);
+        send_inc = 0U;
+    }else if(cec_interrupt_flag_get(CEC_INTF_TBR)){
+        /* set EOM bit if the byte to be transmitted is the last one of the senddata */
+        if(send_inc++ == (bytenum - 1U)){
+            cec_transmission_end();
+            cec_data_send(*transdata++);
+        }else{
+            /* send the byte in the transdata */
+            cec_data_send(*transdata++);
+        }
+        cec_interrupt_flag_clear(CEC_INTF_TBR);
+    }
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CEC/Intercommunication/gd32f1x0_it.h

@@ -0,0 +1,44 @@
+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* NMI handle function */
+void NMI_Handler(void);
+/* HardFault handle function */
+void HardFault_Handler(void);
+/* MemManage handle function */
+void MemManage_Handler(void);
+/* BusFault handle function */
+void BusFault_Handler(void);
+/* UsageFault handle function */
+void UsageFault_Handler(void);
+/* SVC handle function */
+void SVC_Handler(void);
+/* DebugMon handle function */
+void DebugMon_Handler(void);
+/* PendSV handle function */
+void PendSV_Handler(void);
+/* SysTick handle function */
+void SysTick_Handler(void);
+/* EXTI4_15 handle function */
+void EXTI4_15_IRQHandler(void);
+/* CEC handle function */
+void CEC_IRQHandler(void);
+
+#endif /* GD32F1X0_IT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CEC/Intercommunication/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CEC/Intercommunication/main.c

@@ -0,0 +1,127 @@
+/*!
+    \file  main.c
+    \brief CEC intercommunication
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdlib.h>
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+#include "systick.h"
+
+void cec_config(void);
+
+extern uint8_t rcvdata[10];
+extern __IO uint8_t rcvstatus;
+extern uint8_t rcv_inc;
+extern uint8_t bytenum;
+__IO uint8_t NUM=0U;
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* GPIO clock enable */
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_GPIOB);
+    rcu_periph_clock_enable(RCU_GPIOC);
+    rcu_periph_clock_enable(RCU_GPIOF);
+
+    /* delay time initialize */
+    systick_config();
+
+    /* configure the CEC peripheral */
+    cec_config();
+
+    /* configure the EXTI */
+    gd_eval_key_init(KEY_TAMPER, KEY_MODE_EXTI);
+    
+#ifdef GD32F130_150
+    
+    gd_eval_key_init(KEY_USER, KEY_MODE_EXTI);
+
+#elif defined(GD32F170_190)
+    
+    gd_eval_key_init(KEY_WAKEUP, KEY_MODE_EXTI);
+    
+#endif /* GD32F130_150 */
+
+    /* LED1 LED2 initialize */
+    gd_eval_led_init(LED1);
+    gd_eval_led_init(LED2);
+    gd_eval_led_off(LED1);
+    gd_eval_led_off(LED2);
+
+    /* main loop */
+    while(1){
+        /* wait receive data */
+        while(rcvstatus==0U);
+
+        if(rcvstatus == 1U){
+            if((rcvdata[1]==0xA5U)&&(rcvdata[2]==0x5AU)){
+                gd_eval_led_on(LED1);
+                delay_1ms(50U);
+                gd_eval_led_off(LED1);
+            }
+            if((rcvdata[1]==0x5AU)&&(rcvdata[2]==0xA5U)){
+                gd_eval_led_on(LED2);
+                delay_1ms(50U);
+                gd_eval_led_off(LED2);
+            }
+        }
+        /* a reception error occured */
+        rcvstatus = 0U;
+    }
+}
+
+/*!
+    \brief      configure the CEC peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void cec_config(void)
+{
+    /* enable clocks */
+    rcu_periph_clock_enable(RCU_GPIOB);
+    rcu_periph_clock_enable(RCU_CEC);
+
+    /* configure CEC_LINE_GPIO as output open drain */
+    gpio_mode_set(GPIOB,GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO_PIN_8);
+    gpio_output_options_set(GPIOB,GPIO_OTYPE_OD,GPIO_OSPEED_50MHZ,GPIO_PIN_8);
+    gpio_af_set(GPIOB,GPIO_AF_0,GPIO_PIN_8);
+
+    /* configure priority group */
+    nvic_priority_group_set(NVIC_PRIGROUP_PRE1_SUB3);
+
+    /* enable the CEC global interrupt (with higher priority) */
+    nvic_irq_enable(CEC_IRQn,0U,0U);
+
+    /* configure CEC */
+    cec_init(CEC_SFT_START_STAOM,CEC_SFT_1POINT5_PERIOD,CEC_OWN_ADDRESS2);
+    cec_error_config(CEC_BROADCAST_ERROR_BIT_OFF,CEC_LONG_PERIOD_ERROR_BIT_OFF,CEC_RISING_PERIOD_ERROR_BIT_OFF,CEC_STOP_RISING_ERROR_BIT_OFF);
+    cec_reception_tolerance_disable();
+
+    /* activate CEC interrupts associated to the set of TX and RX flags */
+    cec_interrupt_enable(CEC_INTEN_TENDIE | CEC_INTEN_TBRIE | CEC_INTEN_RENDIE | CEC_INTEN_BRIE);
+
+    /* activate CEC interrupts associated to the set of TX and RX error */
+    cec_interrupt_enable(CEC_INTEN_ROIE | CEC_INTEN_BREIE | CEC_INTEN_BPSEIE | CEC_INTEN_BPLEIE 
+    | CEC_INTEN_RAEIE | CEC_INTEN_ARBFIE | CEC_INTEN_TUIE | CEC_INTEN_TERRIE | CEC_INTEN_TAERRIE );
+
+    /* enable CEC */
+    cec_enable();
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CEC/Intercommunication/readme.txt

@@ -0,0 +1,19 @@
+/*!
+    \file  readme.txt
+    \brief description of CEC intercommunication
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+  This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to 
+configure and use the CEC peripheral to receive and transmit messages. In this 
+demo, the same program is loaded to two GD32150R-EVAL/GD32190R-EVAL boards, 
+then they are communicated through connecting respective CEC line(PB8) and GND.
+When press the buttons(K3 or K4) on one board, LED1 and LED2 will blink once.
+  Connect two GD32150R-EVAL/GD32190R-EVAL boards through CEC line(PB8) and GND.

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CEC/Intercommunication/systick.c

@@ -0,0 +1,61 @@
+/*!
+    \file  systick.c
+    \brief the systick configuration file
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include "systick.h"
+
+static uint32_t delay;
+
+/*!
+    \brief      configure systick
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void systick_config(void)
+{
+    /* setup systick timer for 1000Hz interrupts */
+    if (SysTick_Config(SystemCoreClock / 1000)){
+        /* capture error */
+        while (1);
+    }
+    /* configure the systick handler priority */
+    NVIC_SetPriority(SysTick_IRQn, 0x00);
+}
+
+/*!
+    \brief      delay a time in milliseconds
+    \param[in]  count: count in milliseconds
+    \param[out] none
+    \retval     none
+*/
+void delay_1ms(uint32_t count)
+{
+    delay = count;
+
+    while(0 != delay);
+}
+
+/*!
+    \brief      delay decrement
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void delay_decrement(void)
+{
+    if (0 != delay){ 
+        delay--;
+    }
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CEC/Intercommunication/systick.h

@@ -0,0 +1,27 @@
+/*!
+    \file  systick.h
+    \brief the header file of systick
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef SYS_TICK_H
+#define SYS_TICK_H
+
+#include <stdint.h>
+
+/* configure systick */
+void systick_config(void);
+/* delay a time in milliseconds */
+void delay_1ms(uint32_t count);
+/* delay decrement */
+void delay_decrement(void);
+
+#endif /* SYS_TICK_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Interrupt/gd32f1x0_it.c

@@ -0,0 +1,128 @@
+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+#include "gd32f1x0_eval.h"
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+}
+/*!
+    \brief      this function handles External lines 21 and 22 interrupt exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void ADC_CMP_IRQHandler(void)
+{
+    if(RESET != exti_interrupt_flag_get(EXTI_21)){
+        gd_eval_led_on(LED2);
+        exti_interrupt_flag_clear(EXTI_21);
+    }
+}
+

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Interrupt/gd32f1x0_it.h

@@ -0,0 +1,44 @@
+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* NMI handle function */
+void NMI_Handler(void);
+/* HardFault handle function */
+void HardFault_Handler(void);
+/* MemManage handle function */
+void MemManage_Handler(void);
+/* BusFault handle function */
+void BusFault_Handler(void);
+/* UsageFault handle function */
+void UsageFault_Handler(void);
+/* SVC handle function */
+void SVC_Handler(void);
+/* DebugMon handle function */
+void DebugMon_Handler(void);
+/* PendSV handle function */
+void PendSV_Handler(void);
+/* SysTick handle function */
+void SysTick_Handler(void);
+/* ADC CMP handle function */
+void ADC_CMP_IRQHandler(void);
+
+#endif /* GD32F1X0_IT_H */
+
+

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Interrupt/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Interrupt/main.c

@@ -0,0 +1,70 @@
+/*!
+    \file  main.c
+    \brief comparator trigger interrupt using an external interrupt line
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+
+void led_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* configure leds */
+    led_config();
+    
+    /* enable GPIOA clock */
+    rcu_periph_clock_enable(RCU_GPIOA);
+    
+    /* configure PA1 as comparator input */
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_1);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_PULLUP, GPIO_PIN_1);
+    
+    /* enable comparator clock */
+    rcu_periph_clock_enable(RCU_CFGCMP);
+    
+    /* configure CMP0 */
+    cmp_mode_init(CMP0, CMP_VERYLOWSPEED, CMP_1_4VREFINT, CMP_HYSTERESIS_NO);
+    cmp_output_init(CMP0, CMP_OUTPUT_NONE, CMP_OUTPUT_POLARITY_NOINVERTED);
+    
+    /* initialize exti line21 */
+    exti_init(EXTI_21, EXTI_INTERRUPT, EXTI_TRIG_RISING);
+    
+    /* configure ADC_CMP NVIC */
+    nvic_irq_enable(ADC_CMP_IRQn, 0, 0);
+    
+    /* enable CMP0 */
+    cmp_enable(CMP0);
+    
+    while(1);
+}
+
+/*!
+    \brief      configure the leds
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void led_config(void)
+{
+    gd_eval_led_init(LED1);
+    gd_eval_led_init(LED2);
+    gd_eval_led_init(LED3);
+    gd_eval_led_init(LED4);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Interrupt/readme.txt

@@ -0,0 +1,21 @@
+/*!
+    \file  readme.txt
+    \brief description of the comparator interrupt demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to 
+configure the comparator trigger interrupt using an external interrupt line. 
+In this demo,input 3.3V(GD32150R) or 5V(GD32190R)to PA1, EXTI line 21 is 
+configured to generate an interrupt on rising edge of the output signal. After 
+system start-up, enable comparator and trigger interrupt, then LED2 is on. 
+
+  Connect PA1 to +3V3 or +5V.

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/PWM_signal_control/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/PWM_signal_control/main.c

@@ -0,0 +1,124 @@
+/*!
+    \file  main.c
+    \brief PWM output by using comparator output
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+
+uint16_t period = 65535;
+
+void rcu_config(void);
+void gpio_config(void);
+void timer_config(void);
+void cmp_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* configure RCU */
+    rcu_config();
+    
+    /* configure GPIO */
+    gpio_config();
+    
+    /* configure TIMER */
+    timer_config();
+    
+    /* configure comparator */
+    cmp_config();
+    
+    while(1);
+}
+
+/*!
+    \brief      configure RCU
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_GPIOB);
+    rcu_periph_clock_enable(RCU_TIMER1);
+    rcu_periph_clock_enable(RCU_CFGCMP);
+}
+
+/*!
+    \brief      configure GPIO
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* configure PB3 as PWM output */
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3);
+    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_3);
+    gpio_af_set(GPIOB, GPIO_AF_2, GPIO_PIN_3);
+    
+    /* configure PA1 as comparator input */
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_1);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_PULLUP, GPIO_PIN_1);
+    
+}
+
+/*!
+    \brief      configure TIMER
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void timer_config(void)
+{
+    /* initialize TIMER1 */
+    timer_parameter_struct timer_init_parameter;
+    timer_init_parameter.prescaler = 71;
+    timer_init_parameter.counterdirection = TIMER_COUNTER_UP;
+    timer_init_parameter.period = 65535;
+    timer_init_parameter.clockdivision = TIMER_CKDIV_DIV1;
+    
+    timer_init(TIMER1, &timer_init_parameter);
+
+    /* PWM1 mode configure channel1 in PWM1 mode */
+    timer_channel_output_mode_config(TIMER1, TIMER_CH_1, TIMER_OC_MODE_PWM1);
+    timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, (period/2) + 1);
+    timer_channel_output_state_config(TIMER1,TIMER_CH_1, TIMER_CCX_ENABLE);
+    /* select OCREFCLR as source for clearing OC2REF */
+    timer_channel_output_clear_config(TIMER1, TIMER_CH_1, TIMER_OC_CLEAR_ENABLE);
+    timer_ocpre_clear_source_config(TIMER1, TIMER_OCPRE_CLEAR_SOURCE_CLR);
+
+    /* enable TIMER1 counter */
+    timer_enable(TIMER1);
+}
+
+/*!
+    \brief      configure comparator
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void cmp_config(void)
+{
+    /* configure CMP0 */
+    cmp_mode_init(CMP0, CMP_HIGHSPEED, CMP_VREFINT, CMP_HYSTERESIS_NO);
+    cmp_output_init(CMP0, CMP_OUTPUT_TIMER1OCPRECLR, CMP_OUTPUT_POLARITY_NOINVERTED);
+    
+    /* enable CMP0 */
+    cmp_enable(CMP0);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/PWM_signal_control/readme.txt

@@ -0,0 +1,26 @@
+/*!
+    \file  readme.txt
+    \brief description of the comparator pwm signal control demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to 
+  control PWM output by using comparator output
+
+  - CMP channel0 is configured as following:
+  - Inverting input is internally connected to VREFINT = 1.22V
+  - Non Inverting input is connected to PC1(GD32150R)/PC0(GD32190R)
+  - Output is internally connected to TIMER1 OCREFCLR (output compare reference clear)
+
+  - While PC1/PC0 is lower than VREFINT (1.22V), PWM signal is displayed on PB3 
+  - While PC1/PC0 is higher than VREFINT, PB3 is displayed in low level.
+
+  Connect PA1 to PC1(GD32150R)/PC0(GD32190R).

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Port_output/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Port_output/main.c

@@ -0,0 +1,86 @@
+/*!
+    \file  main.c
+    \brief comparator portoutput
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+
+void rcu_config(void);
+void gpio_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    int i;
+    /* configure RCU */
+    rcu_config();
+    
+    /* configure GPIO */
+    gpio_config();
+    
+    gd_eval_led_init(LED2);
+    
+    /* configure CMP0 */
+    cmp_mode_init(CMP0, CMP_VERYLOWSPEED, CMP_1_4VREFINT, CMP_HYSTERESIS_NO);
+    cmp_output_init(CMP0, CMP_OUTPUT_NONE, CMP_OUTPUT_POLARITY_NOINVERTED);
+    
+    /* enable CMP0 */
+    cmp_enable(CMP0);
+    
+    for(i=0; i<100; i++);
+    
+    /* get the output level */
+    if(CMP_OUTPUTLEVEL_HIGH == cmp_output_level_get(CMP0)){
+        gd_eval_led_on(LED2);
+    }else{
+        gd_eval_led_off(LED2);
+    }
+    
+    while (1);
+}
+
+/*!
+    \brief      configure RCU 
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable GPIOA clock */
+    rcu_periph_clock_enable(RCU_GPIOA);
+    /* enable comparator clock */
+    rcu_periph_clock_enable(RCU_CFGCMP);
+}
+
+/*!
+    \brief      configure GPIO
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_1);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_PULLUP, GPIO_PIN_1);
+
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_6);
+    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_6);
+    gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_6);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Port_output/readme.txt

@@ -0,0 +1,19 @@
+/*!
+    \file  readme.txt
+    \brief description of the comparator port output demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to 
+configure the comparator portoutput. In this demo, input 3.3V(GD32150R) or 5V
+(GD32190R) to PA1. After system start-up,enable comparator ,then LED2 is on.
+
+  Connect PA1 to +3V3(GD32150R) or +5V(GD32190R). 

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Switch/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Switch/main.c

@@ -0,0 +1,97 @@
+/*!
+    \file  main.c
+    \brief comparator switch
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+
+void rcu_config(void);
+void gpio_config(void);
+void dac_config(void);
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* configure RCU */
+    rcu_config();
+    
+    /* configure GPIO */
+    gpio_config();
+    
+    /* configure DAC */
+    dac_config();
+    
+    /* set data for DAC0 */
+    dac0_data_set(DAC_ALIGN_12B_R, 0xA00);
+    
+    dac0_software_trigger_enable();
+    
+    /* configure CMP0 */
+    cmp_mode_init(CMP0, CMP_VERYLOWSPEED, CMP_1_2VREFINT, CMP_HYSTERESIS_NO);
+    cmp_output_init(CMP0, CMP_OUTPUT_NONE, CMP_OUTPUT_POLARITY_NOINVERTED);
+    
+    /* enable CMP0 switch */
+    cmp_switch_enable();
+    
+    /* enable CMP0 */
+    cmp_enable(CMP0);
+    
+    while(1);
+}
+
+/*!
+    \brief      configure RCU
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_DAC);
+    rcu_periph_clock_enable(RCU_CFGCMP);
+}
+
+/*!
+    \brief      configure GPIO
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* configure PA4 */
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_4);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_PULLUP, GPIO_PIN_4);
+    /* configure PA6 */
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_6);
+    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_6);
+    gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_6);
+}
+
+/*!
+    \brief      configure dac
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_config(void)
+{
+    dac0_trigger_source_config(DAC_TRIGGER_SOFTWARE);
+    dac0_output_buffer_enable();
+    dac0_enable();
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Switch/readme.txt

@@ -0,0 +1,21 @@
+/*!
+    \file  readme.txt
+    \brief description of the comparator switch demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to
+configure the comparator input switch. In this demo, input 3.3V(GD32150R) or 5V
+(GD32190R) to PA4 ,turn on comparator input switch,then PA4 will be connected to 
+CMP1_IP.After system start-up, enable comparator,then LED2 is on.
+
+  Connect PA4 to +3V3(GD32150R) or +5V(GD32190R). 
+  Connect PA6 to PC11(GD32150R) or PA12(GD32190R).   

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Timer1_CH3IC/gd32f1x0_it.c

@@ -0,0 +1,128 @@
+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+#include "gd32f1x0_eval.h"
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles timer1 handle exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void TIMER1_IRQHandler(void)
+{
+    if(SET == timer_interrupt_flag_get(TIMER1, TIMER_INT_CH3)){
+        gd_eval_led_on(LED3);
+        timer_interrupt_flag_clear(TIMER1, TIMER_INT_CH3);
+    }
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Timer1_CH3IC/gd32f1x0_it.h

@@ -0,0 +1,44 @@
+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* NMI handle function */
+void NMI_Handler(void);
+/* HardFault handle function */
+void HardFault_Handler(void);
+/* MemManage handle function */
+void MemManage_Handler(void);
+/* BusFault handle function */
+void BusFault_Handler(void);
+/* UsageFault handle function */
+void UsageFault_Handler(void);
+/* SVC handle function */
+void SVC_Handler(void);
+/* DebugMon handle function */
+void DebugMon_Handler(void);
+/* PendSV handle function */
+void PendSV_Handler(void);
+/* SysTick handle function */
+void SysTick_Handler(void);
+/* ADC CMP handle function */
+void ADC_CMP_IRQHandler(void);
+
+#endif /* GD32F1X0_IT_H */
+
+

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Timer1_CH3IC/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Timer1_CH3IC/main.c

@@ -0,0 +1,112 @@
+/*!
+    \file  main.c
+    \brief comparator output timer input capture
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+
+void rcu_config(void);
+void gpio_config(void);
+void timer_config(void);
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* configure RCU */
+    rcu_config();
+    
+    /* configure GPIO */
+    gpio_config();
+    
+    /* configure leds */
+    gd_eval_led_init(LED3);
+    
+    /* configure comparator channel0 */
+    cmp_mode_init(CMP0, CMP_VERYLOWSPEED, CMP_1_4VREFINT, CMP_HYSTERESIS_NO);
+    cmp_output_init(CMP0, CMP_OUTPUT_TIMER1IC3, CMP_OUTPUT_POLARITY_NOINVERTED);
+    
+    /* configure TIMER */
+    timer_config();
+    
+    /* enable CMP0 */
+    cmp_enable(CMP0);
+    while(1);
+}
+
+/*!
+    \brief      configure RCU
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_GPIOB);
+    rcu_periph_clock_enable(RCU_GPIOC);
+    rcu_periph_clock_enable(RCU_TIMER1);
+    rcu_periph_clock_enable(RCU_CFGCMP);
+}
+
+/*!
+    \brief      configure GPIO
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* configure PB11 */
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_11) ;
+    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_11);
+    gpio_af_set(GPIOB, GPIO_AF_2, GPIO_PIN_11);
+
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_1) ;
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_PULLUP, GPIO_PIN_1);
+}
+
+/*!
+    \brief      configure TIMER
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void timer_config(void)
+{
+    /* initialize TIMER1 */
+    timer_parameter_struct timer_init_parameter;
+    timer_init_parameter.prescaler = 0;
+    timer_init_parameter.counterdirection = TIMER_COUNTER_UP;
+    timer_init_parameter.period = 65535;
+    timer_init_parameter.clockdivision = TIMER_CKDIV_DIV1;
+    
+    timer_init(TIMER1, &timer_init_parameter);
+    
+    /* clear flag */
+    timer_flag_clear(TIMER1, TIMER_FLAG_UP);
+    
+    nvic_irq_enable(TIMER1_IRQn, 0, 0);
+    
+    /* reset TIMER1 interrupt flag register */
+    TIMER_INTF(TIMER1) = 0;
+    
+    timer_interrupt_enable(TIMER1, TIMER_INT_CH3);
+    
+    /* enable TIMER1 counter */
+    timer_enable(TIMER1);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Timer1_CH3IC/readme.txt

@@ -0,0 +1,21 @@
+/*!
+    \file  readme.txt
+    \brief description of the comparator output timer input capture demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+    This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to 
+  configure the comparator trigger timer 1 channel 3 input capture event, which 
+  is configured to generate an interrupt on both rising and falling edge of the
+  output signal.In this demo, input 3.3V(GD32150R) or 5V(GD32190R) to CMP1_IP.
+  After system start-up, enable comparator and trigger interrupt,then LED3 is on.  
+
+    Connect PA1 to +3V3(GD32150R) or +5V(GD32190R).   

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Window/gd32f1x0_it.c

@@ -0,0 +1,140 @@
+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+#include "main.h"
+
+extern uint32_t delayms;
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+    if(delayms){
+        delayms--;
+    }
+}
+/*!
+    \brief      this function handles External lines 21 and 22 interrupt exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void ADC_CMP_IRQHandler(void)
+{
+    if((RESET != exti_interrupt_flag_get(EXTI_21)) || RESET != (exti_interrupt_flag_get(EXTI_22))){
+        /* recover the system clock to 72MHz */
+        SystemInit();
+        check_state();
+        /* clear EXTI line21 bit */
+        exti_interrupt_flag_clear(EXTI_21);
+        /* clear EXTI line22 bit */
+        exti_interrupt_flag_clear(EXTI_22);
+    }
+}
+
+
+

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Window/gd32f1x0_it.h

@@ -0,0 +1,42 @@
+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* NMI handle function */
+void NMI_Handler(void);
+/* HardFault handle function */
+void HardFault_Handler(void);
+/* MemManage handle function */
+void MemManage_Handler(void);
+/* BusFault handle function */
+void BusFault_Handler(void);
+/* UsageFault handle function */
+void UsageFault_Handler(void);
+/* SVC handle function */
+void SVC_Handler(void);
+/* DebugMon handle function */
+void DebugMon_Handler(void);
+/* PendSV handle function */
+void PendSV_Handler(void);
+/* SysTick handle function */
+void SysTick_Handler(void);
+/* ADC CMP handle function */
+void ADC_CMP_IRQHandler(void);
+
+#endif /* GD32F1X0_IT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Window/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Window/main.c

@@ -0,0 +1,185 @@
+/*!
+    \file  main.c
+    \brief comparator watchdog window
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+#include "main.h"
+
+uint32_t delayms;
+
+void led_config(void);
+void deepsleep_mode_config(void);
+void cmp_config(void);
+void delay_ms(uint32_t time);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    SysTick_Config(72000000/1000);
+    
+    /* configure leds */
+    led_config();
+
+    /* configure CMP0 and CMP1 */
+    cmp_config();
+    
+    /* configure CMP0 and CMP1 */
+    check_state();
+    
+    while(1)
+    {
+        /* input voltage is over the thresholds: higher and lower thresholds */
+        if(STATE_OVER_THRESHOLD == check_state()){
+            gd_eval_led_on(LED1);
+            gd_eval_led_off(LED2);
+            gd_eval_led_on(LED3);
+            gd_eval_led_off(LED4);
+        }
+        /* input voltage is within the thresholds: higher and lower thresholds */
+        if(STATE_WITHIN_THRESHOLD == check_state()){
+            delay_ms(500);
+            if(STATE_WITHIN_THRESHOLD == check_state()){
+                gd_eval_led_off(LED1);
+                gd_eval_led_off(LED2);
+                gd_eval_led_off(LED3);
+                gd_eval_led_off(LED4);
+                /* enter deepsleep mode */
+                deepsleep_mode_config();
+            }
+        }
+        /* input voltage is under the thresholds: higher and lower thresholds */
+        if(STATE_UNDER_THRESHOLD == check_state()){
+            gd_eval_led_off(LED1);
+            gd_eval_led_on(LED2);
+            gd_eval_led_off(LED3);
+            gd_eval_led_on(LED4);
+        }
+    }
+}
+
+/*!
+    \brief      configure comparator
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void cmp_config(void)
+{
+    /* enable GPIOA clock */
+    rcu_periph_clock_enable(RCU_GPIOA);
+    
+    /* configure PA1 as comparator input */
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_1);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_PULLUP, GPIO_PIN_1);
+    
+    /* enable comparator clock */
+    rcu_periph_clock_enable(RCU_CFGCMP);
+    
+    /* configure CMP0 */
+    cmp_mode_init(CMP0, CMP_LOWSPEED, CMP_VREFINT, CMP_HYSTERESIS_HIGH);
+    cmp_output_init(CMP0, CMP_OUTPUT_NONE, CMP_OUTPUT_POLARITY_NOINVERTED);
+    
+    /* configure CMP1 */
+    cmp_mode_init(CMP1, CMP_LOWSPEED, CMP_1_2VREFINT, CMP_HYSTERESIS_HIGH);
+    cmp_output_init(CMP1, CMP_OUTPUT_NONE, CMP_OUTPUT_POLARITY_NOINVERTED);
+    
+    /* configure exti line */
+    exti_init(EXTI_21, EXTI_INTERRUPT, EXTI_TRIG_BOTH);
+    exti_init(EXTI_22, EXTI_INTERRUPT, EXTI_TRIG_BOTH);
+    
+    /* configure ADC_CMP nvic */
+    nvic_irq_enable(ADC_CMP_IRQn, 0, 0);
+    
+    /* enable comparator window */
+    cmp_window_enable();
+    
+    /* enable comparator channels */
+    cmp_enable(CMP0);
+    cmp_enable(CMP1);
+}
+
+/*!
+    \brief      configure deepsleep mode
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void deepsleep_mode_config(void)  
+{
+    /* enable pmu clock */
+    rcu_periph_clock_enable(RCU_PMU);
+
+   /* enter to deepsleep mode */
+    pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD);  
+}
+
+/*!
+    \brief      check comparator output state
+    \param[in]  none
+    \param[out] none
+    \retval     cmp_state
+*/
+cmp_state_enum check_state(void)
+{
+    cmp_state_enum state;
+
+    /* check if cmp0 output level is high and cmp1 output level is high */
+    if ((cmp_output_level_get(CMP0) == CMP_OUTPUTLEVEL_HIGH)
+    && (cmp_output_level_get(CMP1) == CMP_OUTPUTLEVEL_HIGH)){
+        state = STATE_OVER_THRESHOLD;
+    }
+    /* check if cmp0 output level is low and cmp1 output level is high */
+    if ((cmp_output_level_get(CMP0) == CMP_OUTPUTLEVEL_LOW) 
+    && (cmp_output_level_get(CMP1) == CMP_OUTPUTLEVEL_HIGH)){
+        state = STATE_WITHIN_THRESHOLD;
+    }
+    /* check if cmp0 output level is low and cmp1 output level is low */
+    if ((cmp_output_level_get(CMP0) == CMP_OUTPUTLEVEL_LOW)
+    && (cmp_output_level_get(CMP1) == CMP_OUTPUTLEVEL_LOW)){
+        state = STATE_UNDER_THRESHOLD;
+    }
+    return state;
+}
+
+/*!
+    \brief      delay function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void delay_ms(uint32_t time)
+{
+    delayms = time;
+    while(delayms);
+}
+
+/*!
+    \brief      configure the leds
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void led_config(void)
+{
+    gd_eval_led_init(LED1);
+    gd_eval_led_init(LED2);
+    gd_eval_led_init(LED3);
+    gd_eval_led_init(LED4);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Window/main.h

@@ -0,0 +1,27 @@
+/*!
+    \file  main.c
+    \brief the header file of the main
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef MAIN_H
+#define MAIN_H
+
+typedef enum
+{
+    STATE_OVER_THRESHOLD ,
+    STATE_WITHIN_THRESHOLD, 
+    STATE_UNDER_THRESHOLD 
+} cmp_state_enum;
+
+cmp_state_enum check_state(void);
+
+#endif /* MAIN_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Window/readme.txt

@@ -0,0 +1,27 @@
+/*!
+    \file  readme.txt
+    \brief description of the comparator window demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to make 
+  an analog watchdog by using comparator 
+  peripherals in window mode:
+  - The upper threshold is set to VREFINT = 1.22V
+  - The lower threshold is set to VREFINT / 2 = 1.22V = 0.610V
+  - The input voltage is configured to be connected to PC1(GD32150R) or PC0(GD32190R) 
+
+  If the input voltage is above the higher threshold, LED1 and LED3 are turned on.
+  If the input voltage is under the lower threshold, LED2 and LED4 are turned on.
+  If the input voltage is within the thresholds, the MCU remains in deepsleep mode
+  and all leds are turned off.
+
+  Connect PA1 to PC1(GD32150R) or PC0(GD32190R).   

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CRC/Calculate_demo/gd32f1x0_it.c

@@ -0,0 +1,113 @@
+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CRC/Calculate_demo/gd32f1x0_it.h

@@ -0,0 +1,40 @@
+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* NMI handle function */
+void NMI_Handler(void);
+/* HardFault handle function */
+void HardFault_Handler(void);
+/* MemManage handle function */
+void MemManage_Handler(void);
+/* BusFault handle function */
+void BusFault_Handler(void);
+/* UsageFault handle function */
+void UsageFault_Handler(void);
+/* SVC handle function */
+void SVC_Handler(void);
+/* DebugMon handle function */
+void DebugMon_Handler(void);
+/* PendSV handle function */
+void PendSV_Handler(void);
+/* SysTick handle function */
+void SysTick_Handler(void);
+
+#endif /* GD32F1X0_IT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CRC/Calculate_demo/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CRC/Calculate_demo/main.c

@@ -0,0 +1,80 @@
+/*!
+    \file  main.c
+    \brief CRC calculate demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include "systick.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+
+uint32_t vab1 = 0, success_flag = 0;
+uint32_t read32_1, read32_2, read32_3, read32_4, read32_5, read32_6, read32_7, read32_8;
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    gd_eval_led_init(LED1);
+
+    vab1 = (uint32_t)0xabcd1234;
+    rcu_periph_clock_enable(RCU_CRC);
+    
+    crc_deinit();
+    read32_1 = crc_single_data_calculate(vab1);
+
+    /* input reverse */
+    crc_deinit();
+    crc_input_data_reverse_config(CRC_INPUT_DATA_BYTE);
+    read32_2 = crc_single_data_calculate(vab1);
+
+    crc_deinit();
+    crc_input_data_reverse_config(CRC_INPUT_DATA_HALFWORD);
+    read32_3 = crc_single_data_calculate(vab1);
+
+    crc_deinit();
+    crc_input_data_reverse_config(CRC_INPUT_DATA_WORD);
+    read32_4 = crc_single_data_calculate(vab1);
+
+    /* output reverse */
+    crc_deinit();
+    crc_reverse_output_data_enable();
+    read32_5 = crc_single_data_calculate(vab1);
+
+    crc_deinit();
+    crc_input_data_reverse_config(CRC_INPUT_DATA_BYTE);
+    crc_reverse_output_data_enable();
+    read32_6 = crc_single_data_calculate(vab1);
+
+    crc_deinit();
+    crc_input_data_reverse_config(CRC_INPUT_DATA_HALFWORD);
+    crc_reverse_output_data_enable();
+    read32_7 = crc_single_data_calculate(vab1);
+
+    crc_deinit();
+    crc_input_data_reverse_config(CRC_INPUT_DATA_WORD);
+    crc_reverse_output_data_enable();
+    read32_8 = crc_single_data_calculate(vab1);
+
+    /* check the caculation result */
+    if((read32_1 == 0xf7018a40)&&(read32_2 == 0x49fc6721)&&(read32_3 == 0x606444e3)&&(read32_4 == 0x16d70081)
+        &&(read32_5 == 0x025180ef)&&(read32_6 == 0x84e63f92)&&(read32_7 == 0xc7222606)&&(read32_8 == 0x8100eb68)){
+        success_flag = 0x1;
+        gd_eval_led_on(LED1);
+    }
+
+    while (1);
+}