Initial commit

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Interrupt/gd32f1x0_it.c

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+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+#include "gd32f1x0_eval.h"
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+}
+/*!
+    \brief      this function handles External lines 21 and 22 interrupt exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void ADC_CMP_IRQHandler(void)
+{
+    if(RESET != exti_interrupt_flag_get(EXTI_21)){
+        gd_eval_led_on(LED2);
+        exti_interrupt_flag_clear(EXTI_21);
+    }
+}
+

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Interrupt/gd32f1x0_it.h

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+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* NMI handle function */
+void NMI_Handler(void);
+/* HardFault handle function */
+void HardFault_Handler(void);
+/* MemManage handle function */
+void MemManage_Handler(void);
+/* BusFault handle function */
+void BusFault_Handler(void);
+/* UsageFault handle function */
+void UsageFault_Handler(void);
+/* SVC handle function */
+void SVC_Handler(void);
+/* DebugMon handle function */
+void DebugMon_Handler(void);
+/* PendSV handle function */
+void PendSV_Handler(void);
+/* SysTick handle function */
+void SysTick_Handler(void);
+/* ADC CMP handle function */
+void ADC_CMP_IRQHandler(void);
+
+#endif /* GD32F1X0_IT_H */
+
+

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Interrupt/gd32f1x0_libopt.h

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+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Interrupt/main.c

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+/*!
+    \file  main.c
+    \brief comparator trigger interrupt using an external interrupt line
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+
+void led_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* configure leds */
+    led_config();
+    
+    /* enable GPIOA clock */
+    rcu_periph_clock_enable(RCU_GPIOA);
+    
+    /* configure PA1 as comparator input */
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_1);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_PULLUP, GPIO_PIN_1);
+    
+    /* enable comparator clock */
+    rcu_periph_clock_enable(RCU_CFGCMP);
+    
+    /* configure CMP0 */
+    cmp_mode_init(CMP0, CMP_VERYLOWSPEED, CMP_1_4VREFINT, CMP_HYSTERESIS_NO);
+    cmp_output_init(CMP0, CMP_OUTPUT_NONE, CMP_OUTPUT_POLARITY_NOINVERTED);
+    
+    /* initialize exti line21 */
+    exti_init(EXTI_21, EXTI_INTERRUPT, EXTI_TRIG_RISING);
+    
+    /* configure ADC_CMP NVIC */
+    nvic_irq_enable(ADC_CMP_IRQn, 0, 0);
+    
+    /* enable CMP0 */
+    cmp_enable(CMP0);
+    
+    while(1);
+}
+
+/*!
+    \brief      configure the leds
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void led_config(void)
+{
+    gd_eval_led_init(LED1);
+    gd_eval_led_init(LED2);
+    gd_eval_led_init(LED3);
+    gd_eval_led_init(LED4);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Interrupt/readme.txt

@@ -0,0 +1,21 @@
+/*!
+    \file  readme.txt
+    \brief description of the comparator interrupt demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to 
+configure the comparator trigger interrupt using an external interrupt line. 
+In this demo,input 3.3V(GD32150R) or 5V(GD32190R)to PA1, EXTI line 21 is 
+configured to generate an interrupt on rising edge of the output signal. After 
+system start-up, enable comparator and trigger interrupt, then LED2 is on. 
+
+  Connect PA1 to +3V3 or +5V.

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/PWM_signal_control/gd32f1x0_libopt.h

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+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/PWM_signal_control/main.c

@@ -0,0 +1,124 @@
+/*!
+    \file  main.c
+    \brief PWM output by using comparator output
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+
+uint16_t period = 65535;
+
+void rcu_config(void);
+void gpio_config(void);
+void timer_config(void);
+void cmp_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* configure RCU */
+    rcu_config();
+    
+    /* configure GPIO */
+    gpio_config();
+    
+    /* configure TIMER */
+    timer_config();
+    
+    /* configure comparator */
+    cmp_config();
+    
+    while(1);
+}
+
+/*!
+    \brief      configure RCU
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_GPIOB);
+    rcu_periph_clock_enable(RCU_TIMER1);
+    rcu_periph_clock_enable(RCU_CFGCMP);
+}
+
+/*!
+    \brief      configure GPIO
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* configure PB3 as PWM output */
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3);
+    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_3);
+    gpio_af_set(GPIOB, GPIO_AF_2, GPIO_PIN_3);
+    
+    /* configure PA1 as comparator input */
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_1);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_PULLUP, GPIO_PIN_1);
+    
+}
+
+/*!
+    \brief      configure TIMER
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void timer_config(void)
+{
+    /* initialize TIMER1 */
+    timer_parameter_struct timer_init_parameter;
+    timer_init_parameter.prescaler = 71;
+    timer_init_parameter.counterdirection = TIMER_COUNTER_UP;
+    timer_init_parameter.period = 65535;
+    timer_init_parameter.clockdivision = TIMER_CKDIV_DIV1;
+    
+    timer_init(TIMER1, &timer_init_parameter);
+
+    /* PWM1 mode configure channel1 in PWM1 mode */
+    timer_channel_output_mode_config(TIMER1, TIMER_CH_1, TIMER_OC_MODE_PWM1);
+    timer_channel_output_pulse_value_config(TIMER1, TIMER_CH_1, (period/2) + 1);
+    timer_channel_output_state_config(TIMER1,TIMER_CH_1, TIMER_CCX_ENABLE);
+    /* select OCREFCLR as source for clearing OC2REF */
+    timer_channel_output_clear_config(TIMER1, TIMER_CH_1, TIMER_OC_CLEAR_ENABLE);
+    timer_ocpre_clear_source_config(TIMER1, TIMER_OCPRE_CLEAR_SOURCE_CLR);
+
+    /* enable TIMER1 counter */
+    timer_enable(TIMER1);
+}
+
+/*!
+    \brief      configure comparator
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void cmp_config(void)
+{
+    /* configure CMP0 */
+    cmp_mode_init(CMP0, CMP_HIGHSPEED, CMP_VREFINT, CMP_HYSTERESIS_NO);
+    cmp_output_init(CMP0, CMP_OUTPUT_TIMER1OCPRECLR, CMP_OUTPUT_POLARITY_NOINVERTED);
+    
+    /* enable CMP0 */
+    cmp_enable(CMP0);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/PWM_signal_control/readme.txt

@@ -0,0 +1,26 @@
+/*!
+    \file  readme.txt
+    \brief description of the comparator pwm signal control demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to 
+  control PWM output by using comparator output
+
+  - CMP channel0 is configured as following:
+  - Inverting input is internally connected to VREFINT = 1.22V
+  - Non Inverting input is connected to PC1(GD32150R)/PC0(GD32190R)
+  - Output is internally connected to TIMER1 OCREFCLR (output compare reference clear)
+
+  - While PC1/PC0 is lower than VREFINT (1.22V), PWM signal is displayed on PB3 
+  - While PC1/PC0 is higher than VREFINT, PB3 is displayed in low level.
+
+  Connect PA1 to PC1(GD32150R)/PC0(GD32190R).

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Port_output/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Port_output/main.c

@@ -0,0 +1,86 @@
+/*!
+    \file  main.c
+    \brief comparator portoutput
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+
+void rcu_config(void);
+void gpio_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    int i;
+    /* configure RCU */
+    rcu_config();
+    
+    /* configure GPIO */
+    gpio_config();
+    
+    gd_eval_led_init(LED2);
+    
+    /* configure CMP0 */
+    cmp_mode_init(CMP0, CMP_VERYLOWSPEED, CMP_1_4VREFINT, CMP_HYSTERESIS_NO);
+    cmp_output_init(CMP0, CMP_OUTPUT_NONE, CMP_OUTPUT_POLARITY_NOINVERTED);
+    
+    /* enable CMP0 */
+    cmp_enable(CMP0);
+    
+    for(i=0; i<100; i++);
+    
+    /* get the output level */
+    if(CMP_OUTPUTLEVEL_HIGH == cmp_output_level_get(CMP0)){
+        gd_eval_led_on(LED2);
+    }else{
+        gd_eval_led_off(LED2);
+    }
+    
+    while (1);
+}
+
+/*!
+    \brief      configure RCU 
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable GPIOA clock */
+    rcu_periph_clock_enable(RCU_GPIOA);
+    /* enable comparator clock */
+    rcu_periph_clock_enable(RCU_CFGCMP);
+}
+
+/*!
+    \brief      configure GPIO
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_1);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_PULLUP, GPIO_PIN_1);
+
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_6);
+    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_6);
+    gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_6);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Port_output/readme.txt

@@ -0,0 +1,19 @@
+/*!
+    \file  readme.txt
+    \brief description of the comparator port output demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to 
+configure the comparator portoutput. In this demo, input 3.3V(GD32150R) or 5V
+(GD32190R) to PA1. After system start-up,enable comparator ,then LED2 is on.
+
+  Connect PA1 to +3V3(GD32150R) or +5V(GD32190R). 

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Switch/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Switch/main.c

@@ -0,0 +1,97 @@
+/*!
+    \file  main.c
+    \brief comparator switch
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+
+void rcu_config(void);
+void gpio_config(void);
+void dac_config(void);
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* configure RCU */
+    rcu_config();
+    
+    /* configure GPIO */
+    gpio_config();
+    
+    /* configure DAC */
+    dac_config();
+    
+    /* set data for DAC0 */
+    dac0_data_set(DAC_ALIGN_12B_R, 0xA00);
+    
+    dac0_software_trigger_enable();
+    
+    /* configure CMP0 */
+    cmp_mode_init(CMP0, CMP_VERYLOWSPEED, CMP_1_2VREFINT, CMP_HYSTERESIS_NO);
+    cmp_output_init(CMP0, CMP_OUTPUT_NONE, CMP_OUTPUT_POLARITY_NOINVERTED);
+    
+    /* enable CMP0 switch */
+    cmp_switch_enable();
+    
+    /* enable CMP0 */
+    cmp_enable(CMP0);
+    
+    while(1);
+}
+
+/*!
+    \brief      configure RCU
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_DAC);
+    rcu_periph_clock_enable(RCU_CFGCMP);
+}
+
+/*!
+    \brief      configure GPIO
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* configure PA4 */
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_4);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_PULLUP, GPIO_PIN_4);
+    /* configure PA6 */
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_6);
+    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_6);
+    gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_6);
+}
+
+/*!
+    \brief      configure dac
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dac_config(void)
+{
+    dac0_trigger_source_config(DAC_TRIGGER_SOFTWARE);
+    dac0_output_buffer_enable();
+    dac0_enable();
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Switch/readme.txt

@@ -0,0 +1,21 @@
+/*!
+    \file  readme.txt
+    \brief description of the comparator switch demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to
+configure the comparator input switch. In this demo, input 3.3V(GD32150R) or 5V
+(GD32190R) to PA4 ,turn on comparator input switch,then PA4 will be connected to 
+CMP1_IP.After system start-up, enable comparator,then LED2 is on.
+
+  Connect PA4 to +3V3(GD32150R) or +5V(GD32190R). 
+  Connect PA6 to PC11(GD32150R) or PA12(GD32190R).   

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Timer1_CH3IC/gd32f1x0_it.c

@@ -0,0 +1,128 @@
+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+#include "gd32f1x0_eval.h"
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles timer1 handle exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void TIMER1_IRQHandler(void)
+{
+    if(SET == timer_interrupt_flag_get(TIMER1, TIMER_INT_CH3)){
+        gd_eval_led_on(LED3);
+        timer_interrupt_flag_clear(TIMER1, TIMER_INT_CH3);
+    }
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Timer1_CH3IC/gd32f1x0_it.h

@@ -0,0 +1,44 @@
+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* NMI handle function */
+void NMI_Handler(void);
+/* HardFault handle function */
+void HardFault_Handler(void);
+/* MemManage handle function */
+void MemManage_Handler(void);
+/* BusFault handle function */
+void BusFault_Handler(void);
+/* UsageFault handle function */
+void UsageFault_Handler(void);
+/* SVC handle function */
+void SVC_Handler(void);
+/* DebugMon handle function */
+void DebugMon_Handler(void);
+/* PendSV handle function */
+void PendSV_Handler(void);
+/* SysTick handle function */
+void SysTick_Handler(void);
+/* ADC CMP handle function */
+void ADC_CMP_IRQHandler(void);
+
+#endif /* GD32F1X0_IT_H */
+
+

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Timer1_CH3IC/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Timer1_CH3IC/main.c

@@ -0,0 +1,112 @@
+/*!
+    \file  main.c
+    \brief comparator output timer input capture
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+
+void rcu_config(void);
+void gpio_config(void);
+void timer_config(void);
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* configure RCU */
+    rcu_config();
+    
+    /* configure GPIO */
+    gpio_config();
+    
+    /* configure leds */
+    gd_eval_led_init(LED3);
+    
+    /* configure comparator channel0 */
+    cmp_mode_init(CMP0, CMP_VERYLOWSPEED, CMP_1_4VREFINT, CMP_HYSTERESIS_NO);
+    cmp_output_init(CMP0, CMP_OUTPUT_TIMER1IC3, CMP_OUTPUT_POLARITY_NOINVERTED);
+    
+    /* configure TIMER */
+    timer_config();
+    
+    /* enable CMP0 */
+    cmp_enable(CMP0);
+    while(1);
+}
+
+/*!
+    \brief      configure RCU
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_GPIOB);
+    rcu_periph_clock_enable(RCU_GPIOC);
+    rcu_periph_clock_enable(RCU_TIMER1);
+    rcu_periph_clock_enable(RCU_CFGCMP);
+}
+
+/*!
+    \brief      configure GPIO
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* configure PB11 */
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_11) ;
+    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_11);
+    gpio_af_set(GPIOB, GPIO_AF_2, GPIO_PIN_11);
+
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_1) ;
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_PULLUP, GPIO_PIN_1);
+}
+
+/*!
+    \brief      configure TIMER
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void timer_config(void)
+{
+    /* initialize TIMER1 */
+    timer_parameter_struct timer_init_parameter;
+    timer_init_parameter.prescaler = 0;
+    timer_init_parameter.counterdirection = TIMER_COUNTER_UP;
+    timer_init_parameter.period = 65535;
+    timer_init_parameter.clockdivision = TIMER_CKDIV_DIV1;
+    
+    timer_init(TIMER1, &timer_init_parameter);
+    
+    /* clear flag */
+    timer_flag_clear(TIMER1, TIMER_FLAG_UP);
+    
+    nvic_irq_enable(TIMER1_IRQn, 0, 0);
+    
+    /* reset TIMER1 interrupt flag register */
+    TIMER_INTF(TIMER1) = 0;
+    
+    timer_interrupt_enable(TIMER1, TIMER_INT_CH3);
+    
+    /* enable TIMER1 counter */
+    timer_enable(TIMER1);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Timer1_CH3IC/readme.txt

@@ -0,0 +1,21 @@
+/*!
+    \file  readme.txt
+    \brief description of the comparator output timer input capture demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+    This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to 
+  configure the comparator trigger timer 1 channel 3 input capture event, which 
+  is configured to generate an interrupt on both rising and falling edge of the
+  output signal.In this demo, input 3.3V(GD32150R) or 5V(GD32190R) to CMP1_IP.
+  After system start-up, enable comparator and trigger interrupt,then LED3 is on.  
+
+    Connect PA1 to +3V3(GD32150R) or +5V(GD32190R).   

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Window/gd32f1x0_it.c

@@ -0,0 +1,140 @@
+/*!
+    \file  gd32f1x0_it.c
+    \brief interrupt service routines
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0_it.h"
+#include "main.h"
+
+extern uint32_t delayms;
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1);
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+    if(delayms){
+        delayms--;
+    }
+}
+/*!
+    \brief      this function handles External lines 21 and 22 interrupt exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void ADC_CMP_IRQHandler(void)
+{
+    if((RESET != exti_interrupt_flag_get(EXTI_21)) || RESET != (exti_interrupt_flag_get(EXTI_22))){
+        /* recover the system clock to 72MHz */
+        SystemInit();
+        check_state();
+        /* clear EXTI line21 bit */
+        exti_interrupt_flag_clear(EXTI_21);
+        /* clear EXTI line22 bit */
+        exti_interrupt_flag_clear(EXTI_22);
+    }
+}
+
+
+

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Window/gd32f1x0_it.h

@@ -0,0 +1,42 @@
+/*!
+    \file  gd32f1x0_it.h
+    \brief the header file of the ISR
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_IT_H
+#define GD32F1X0_IT_H
+
+#include "gd32f1x0.h"
+
+/* function declarations */
+/* NMI handle function */
+void NMI_Handler(void);
+/* HardFault handle function */
+void HardFault_Handler(void);
+/* MemManage handle function */
+void MemManage_Handler(void);
+/* BusFault handle function */
+void BusFault_Handler(void);
+/* UsageFault handle function */
+void UsageFault_Handler(void);
+/* SVC handle function */
+void SVC_Handler(void);
+/* DebugMon handle function */
+void DebugMon_Handler(void);
+/* PendSV handle function */
+void PendSV_Handler(void);
+/* SysTick handle function */
+void SysTick_Handler(void);
+/* ADC CMP handle function */
+void ADC_CMP_IRQHandler(void);
+
+#endif /* GD32F1X0_IT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Window/gd32f1x0_libopt.h

@@ -0,0 +1,47 @@
+/*!
+    \file  gd32f1x0_libopt.h
+    \brief library optional for gd32f1x0
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef GD32F1X0_LIBOPT_H
+#define GD32F1X0_LIBOPT_H
+
+#include "gd32f1x0_adc.h"
+#include "gd32f1x0_cec.h"
+#include "gd32f1x0_crc.h"
+#include "gd32f1x0_cmp.h"
+#include "gd32f1x0_dac.h"
+#include "gd32f1x0_dbg.h"
+#include "gd32f1x0_dma.h"
+#include "gd32f1x0_exti.h"
+#include "gd32f1x0_fmc.h"
+#include "gd32f1x0_gpio.h"
+#include "gd32f1x0_syscfg.h"
+#include "gd32f1x0_i2c.h"
+#include "gd32f1x0_fwdgt.h"
+#include "gd32f1x0_pmu.h"
+#include "gd32f1x0_rcu.h"
+#include "gd32f1x0_rtc.h"
+#include "gd32f1x0_spi.h"
+#include "gd32f1x0_timer.h"
+#include "gd32f1x0_usart.h"
+#include "gd32f1x0_wwdgt.h"
+#include "gd32f1x0_misc.h"
+#include "gd32f1x0_tsi.h"
+#ifdef GD32F170_190
+#include "gd32f1x0_slcd.h"
+#include "gd32f1x0_opa.h"
+#include "gd32f1x0_ivref.h"
+#include "gd32f1x0_can.h"
+#endif /* GD32F170_190 */
+
+#endif /* GD32F1X0_LIBOPT_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Window/main.c

@@ -0,0 +1,185 @@
+/*!
+    \file  main.c
+    \brief comparator watchdog window
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#include "gd32f1x0.h"
+#include <stdio.h>
+#include "gd32f1x0_eval.h"
+#include "main.h"
+
+uint32_t delayms;
+
+void led_config(void);
+void deepsleep_mode_config(void);
+void cmp_config(void);
+void delay_ms(uint32_t time);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    SysTick_Config(72000000/1000);
+    
+    /* configure leds */
+    led_config();
+
+    /* configure CMP0 and CMP1 */
+    cmp_config();
+    
+    /* configure CMP0 and CMP1 */
+    check_state();
+    
+    while(1)
+    {
+        /* input voltage is over the thresholds: higher and lower thresholds */
+        if(STATE_OVER_THRESHOLD == check_state()){
+            gd_eval_led_on(LED1);
+            gd_eval_led_off(LED2);
+            gd_eval_led_on(LED3);
+            gd_eval_led_off(LED4);
+        }
+        /* input voltage is within the thresholds: higher and lower thresholds */
+        if(STATE_WITHIN_THRESHOLD == check_state()){
+            delay_ms(500);
+            if(STATE_WITHIN_THRESHOLD == check_state()){
+                gd_eval_led_off(LED1);
+                gd_eval_led_off(LED2);
+                gd_eval_led_off(LED3);
+                gd_eval_led_off(LED4);
+                /* enter deepsleep mode */
+                deepsleep_mode_config();
+            }
+        }
+        /* input voltage is under the thresholds: higher and lower thresholds */
+        if(STATE_UNDER_THRESHOLD == check_state()){
+            gd_eval_led_off(LED1);
+            gd_eval_led_on(LED2);
+            gd_eval_led_off(LED3);
+            gd_eval_led_on(LED4);
+        }
+    }
+}
+
+/*!
+    \brief      configure comparator
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void cmp_config(void)
+{
+    /* enable GPIOA clock */
+    rcu_periph_clock_enable(RCU_GPIOA);
+    
+    /* configure PA1 as comparator input */
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_1);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_PULLUP, GPIO_PIN_1);
+    
+    /* enable comparator clock */
+    rcu_periph_clock_enable(RCU_CFGCMP);
+    
+    /* configure CMP0 */
+    cmp_mode_init(CMP0, CMP_LOWSPEED, CMP_VREFINT, CMP_HYSTERESIS_HIGH);
+    cmp_output_init(CMP0, CMP_OUTPUT_NONE, CMP_OUTPUT_POLARITY_NOINVERTED);
+    
+    /* configure CMP1 */
+    cmp_mode_init(CMP1, CMP_LOWSPEED, CMP_1_2VREFINT, CMP_HYSTERESIS_HIGH);
+    cmp_output_init(CMP1, CMP_OUTPUT_NONE, CMP_OUTPUT_POLARITY_NOINVERTED);
+    
+    /* configure exti line */
+    exti_init(EXTI_21, EXTI_INTERRUPT, EXTI_TRIG_BOTH);
+    exti_init(EXTI_22, EXTI_INTERRUPT, EXTI_TRIG_BOTH);
+    
+    /* configure ADC_CMP nvic */
+    nvic_irq_enable(ADC_CMP_IRQn, 0, 0);
+    
+    /* enable comparator window */
+    cmp_window_enable();
+    
+    /* enable comparator channels */
+    cmp_enable(CMP0);
+    cmp_enable(CMP1);
+}
+
+/*!
+    \brief      configure deepsleep mode
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void deepsleep_mode_config(void)  
+{
+    /* enable pmu clock */
+    rcu_periph_clock_enable(RCU_PMU);
+
+   /* enter to deepsleep mode */
+    pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD);  
+}
+
+/*!
+    \brief      check comparator output state
+    \param[in]  none
+    \param[out] none
+    \retval     cmp_state
+*/
+cmp_state_enum check_state(void)
+{
+    cmp_state_enum state;
+
+    /* check if cmp0 output level is high and cmp1 output level is high */
+    if ((cmp_output_level_get(CMP0) == CMP_OUTPUTLEVEL_HIGH)
+    && (cmp_output_level_get(CMP1) == CMP_OUTPUTLEVEL_HIGH)){
+        state = STATE_OVER_THRESHOLD;
+    }
+    /* check if cmp0 output level is low and cmp1 output level is high */
+    if ((cmp_output_level_get(CMP0) == CMP_OUTPUTLEVEL_LOW) 
+    && (cmp_output_level_get(CMP1) == CMP_OUTPUTLEVEL_HIGH)){
+        state = STATE_WITHIN_THRESHOLD;
+    }
+    /* check if cmp0 output level is low and cmp1 output level is low */
+    if ((cmp_output_level_get(CMP0) == CMP_OUTPUTLEVEL_LOW)
+    && (cmp_output_level_get(CMP1) == CMP_OUTPUTLEVEL_LOW)){
+        state = STATE_UNDER_THRESHOLD;
+    }
+    return state;
+}
+
+/*!
+    \brief      delay function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void delay_ms(uint32_t time)
+{
+    delayms = time;
+    while(delayms);
+}
+
+/*!
+    \brief      configure the leds
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void led_config(void)
+{
+    gd_eval_led_init(LED1);
+    gd_eval_led_init(LED2);
+    gd_eval_led_init(LED3);
+    gd_eval_led_init(LED4);
+}

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Window/main.h

@@ -0,0 +1,27 @@
+/*!
+    \file  main.c
+    \brief the header file of the main
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+#ifndef MAIN_H
+#define MAIN_H
+
+typedef enum
+{
+    STATE_OVER_THRESHOLD ,
+    STATE_WITHIN_THRESHOLD, 
+    STATE_UNDER_THRESHOLD 
+} cmp_state_enum;
+
+cmp_state_enum check_state(void);
+
+#endif /* MAIN_H */

docs/GD32F1x0_Firmware_Library_v3.1.0/Examples/CMP/Window/readme.txt

@@ -0,0 +1,27 @@
+/*!
+    \file  readme.txt
+    \brief description of the comparator window demo
+*/
+
+/*
+    Copyright (C) 2017 GigaDevice
+
+    2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
+    2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
+    2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
+    2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
+*/
+
+  This demo is based on the GD32150R-EVAL/GD32190R-EVAL board, it shows how to make 
+  an analog watchdog by using comparator 
+  peripherals in window mode:
+  - The upper threshold is set to VREFINT = 1.22V
+  - The lower threshold is set to VREFINT / 2 = 1.22V = 0.610V
+  - The input voltage is configured to be connected to PC1(GD32150R) or PC0(GD32190R) 
+
+  If the input voltage is above the higher threshold, LED1 and LED3 are turned on.
+  If the input voltage is under the lower threshold, LED2 and LED4 are turned on.
+  If the input voltage is within the thresholds, the MCU remains in deepsleep mode
+  and all leds are turned off.
+
+  Connect PA1 to PC1(GD32150R) or PC0(GD32190R).