mirror of
https://github.com/EFeru/hoverboard-sideboard-hack-GD.git
synced 2025-08-18 09:36:11 +00:00
Initial commit
This commit is contained in:
EmanuelFeru
@@ -0,0 +1,130 @@
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||||
/*!
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||||
\file gd32f1x0_it.c
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\brief interrupt service routines
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*/
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||||
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/*
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||||
Copyright (C) 2017 GigaDevice
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||||
|
||||
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
|
||||
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
|
||||
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
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||||
*/
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||||
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#include "gd32f1x0_it.h"
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extern __IO uint32_t int_num;
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/*!
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\brief this function handles NMI exception
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\param[in] none
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\param[out] none
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\retval none
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*/
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void NMI_Handler(void)
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{
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}
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/*!
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\brief this function handles HardFault exception
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\param[in] none
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\param[out] none
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\retval none
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*/
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void HardFault_Handler(void)
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{
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/* if Hard Fault exception occurs, go to infinite loop */
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while (1);
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}
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/*!
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\brief this function handles MemManage exception
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\param[in] none
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\param[out] none
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\retval none
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*/
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void MemManage_Handler(void)
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{
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/* if Memory Manage exception occurs, go to infinite loop */
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while (1);
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}
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/*!
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\brief this function handles BusFault exception
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\param[in] none
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\param[out] none
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\retval none
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*/
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void BusFault_Handler(void)
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{
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/* if Bus Fault exception occurs, go to infinite loop */
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while (1);
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}
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/*!
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\brief this function handles UsageFault exception
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\param[in] none
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\param[out] none
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\retval none
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*/
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void UsageFault_Handler(void)
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{
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/* if Usage Fault exception occurs, go to infinite loop */
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while (1);
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}
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/*!
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\brief this function handles SVC exception
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\param[in] none
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\param[out] none
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\retval none
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*/
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void SVC_Handler(void)
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{
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}
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/*!
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\brief this function handles DebugMon exception
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\param[in] none
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\param[out] none
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\retval none
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*/
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void DebugMon_Handler(void)
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{
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}
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/*!
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\brief this function handles PendSV exception
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\param[in] none
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\param[out] none
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\retval none
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*/
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void PendSV_Handler(void)
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{
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}
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/*!
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\brief this function handles SysTick exception
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\param[in] none
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\param[out] none
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\retval none
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*/
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void SysTick_Handler(void)
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{
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}
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/*!
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\brief this function handles DMA_Channel0_IRQHandler interrupt
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\param[in] none
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\param[out] none
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\retval none
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*/
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void DMA_Channel0_IRQHandler(void)
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{
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if(dma_interrupt_flag_get(DMA_CH0,DMA_INT_FLAG_FTF)){
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int_num++;
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dma_interrupt_flag_clear(DMA_CH0,DMA_INT_FLAG_FTF);
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dma_interrupt_flag_clear(DMA_CH0,DMA_INT_FLAG_G);
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}
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}
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@@ -0,0 +1,42 @@
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/*!
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\file gd32f1x0_it.h
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\brief the header file of the ISR
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*/
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/*
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Copyright (C) 2017 GigaDevice
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||||
|
||||
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
|
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2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
|
||||
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
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||||
*/
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#ifndef GD32F1X0_IT_H
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#define GD32F1X0_IT_H
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#include "gd32f1x0.h"
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/* function declarations */
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/* NMI handle function */
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void NMI_Handler(void);
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/* HardFault handle function */
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void HardFault_Handler(void);
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/* MemManage handle function */
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void MemManage_Handler(void);
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/* BusFault handle function */
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void BusFault_Handler(void);
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/* UsageFault handle function */
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void UsageFault_Handler(void);
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/* SVC handle function */
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void SVC_Handler(void);
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/* DebugMon handle function */
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void DebugMon_Handler(void);
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/* PendSV handle function */
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void PendSV_Handler(void);
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/* SysTick handle function */
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void SysTick_Handler(void);
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/* DMA_Channel0 handle function */
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void DMA_Channel0_IRQHandler(void);
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#endif /* GD32F1X0_IT_H */
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@@ -0,0 +1,47 @@
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/*!
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\file gd32f1x0_libopt.h
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\brief library optional for gd32f1x0
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*/
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/*
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Copyright (C) 2017 GigaDevice
|
||||
|
||||
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
|
||||
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
|
||||
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
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||||
*/
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||||
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#ifndef GD32F1X0_LIBOPT_H
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#define GD32F1X0_LIBOPT_H
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#include "gd32f1x0_adc.h"
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#include "gd32f1x0_cec.h"
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#include "gd32f1x0_crc.h"
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#include "gd32f1x0_cmp.h"
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#include "gd32f1x0_dac.h"
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#include "gd32f1x0_dbg.h"
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#include "gd32f1x0_dma.h"
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#include "gd32f1x0_exti.h"
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#include "gd32f1x0_fmc.h"
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#include "gd32f1x0_gpio.h"
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#include "gd32f1x0_syscfg.h"
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#include "gd32f1x0_i2c.h"
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#include "gd32f1x0_fwdgt.h"
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#include "gd32f1x0_pmu.h"
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#include "gd32f1x0_rcu.h"
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#include "gd32f1x0_rtc.h"
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#include "gd32f1x0_spi.h"
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#include "gd32f1x0_timer.h"
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#include "gd32f1x0_usart.h"
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#include "gd32f1x0_wwdgt.h"
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#include "gd32f1x0_misc.h"
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#include "gd32f1x0_tsi.h"
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#ifdef GD32F170_190
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#include "gd32f1x0_slcd.h"
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#include "gd32f1x0_opa.h"
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#include "gd32f1x0_ivref.h"
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#include "gd32f1x0_can.h"
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#endif /* GD32F170_190 */
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#endif /* GD32F1X0_LIBOPT_H */
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@@ -0,0 +1,200 @@
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/*!
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\file main.c
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\brief transfer data from FLASH to RAM
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*/
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/*
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Copyright (C) 2017 GigaDevice
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||||
|
||||
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
|
||||
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
|
||||
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
*/
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#include "gd32f1x0.h"
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#include <stdio.h>
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#include "gd32f1x0_eval.h"
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#define ACCESSSUM 1024
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#define FMC_PAGE_SIZE ((uint16_t)0x400)
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#define BANK1_WRITE_START_ADDR ((uint32_t)0x08004000)
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#define BANK1_WRITE_END_ADDR ((uint32_t)0x08004800)
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void rcu_config(void);
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void nvic_config(void);
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void led_config(void);
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__IO ErrStatus accessflag = SUCCESS;
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uint32_t destdata[256];
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uint32_t *ptrd;
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__IO uint32_t int_num = 0;
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uint32_t erasenum = 0x00, address = 0x00 ,wperror = 0,wperror2 = 0;
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uint32_t transdata = 0x3210ABCD;
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__IO uint32_t pagenum = 0x00;
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volatile fmc_state_enum fmcstatus = FMC_READY;
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/*!
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\brief main function
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\param[in] none
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\param[out] none
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\retval none
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*/
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int main(void)
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{
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uint32_t i;
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dma_parameter_struct dma_init_struct;
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/* system clocks configuration */
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rcu_config();
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/* NVIC configuration */
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nvic_config();
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led_config() ;
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/* unlock the flash bank1 program erase controller */
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fmc_unlock();
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/* define the number of page to be erased */
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pagenum = (BANK1_WRITE_END_ADDR - BANK1_WRITE_START_ADDR) / FMC_PAGE_SIZE;
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/* clear all pending flags */
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fmc_flag_clear(FMC_FLAG_PGERR | FMC_FLAG_WPERR | FMC_FLAG_END);
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/* erase the flash pages */
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for(erasenum = 0; erasenum < pagenum; erasenum++){
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fmcstatus = fmc_page_erase(BANK1_WRITE_START_ADDR + (FMC_PAGE_SIZE * erasenum));
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wperror += (fmcstatus == FMC_WPERR);
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fmc_flag_clear(FMC_FLAG_PGERR | FMC_FLAG_WPERR | FMC_FLAG_END);
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}
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/* unlock the flash bank1 program erase controller */
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fmc_lock();
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ptrd = (uint32_t*)BANK1_WRITE_START_ADDR;
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for(i = 0; i < 256; i++){
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if(0xFFFFFFFF != *ptrd){
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accessflag = ERROR;
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||||
break;
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||||
}
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||||
ptrd++;
|
||||
}
|
||||
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||||
/* unlock the flash bank1 program erase controller */
|
||||
fmc_unlock();
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||||
|
||||
/* define the number of page to be erased */
|
||||
pagenum = (BANK1_WRITE_END_ADDR - BANK1_WRITE_START_ADDR) / FMC_PAGE_SIZE;
|
||||
|
||||
/* clear all pending flags */
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||||
fmc_flag_clear(FMC_FLAG_PGERR | FMC_FLAG_WPERR | FMC_FLAG_END);
|
||||
|
||||
/* program flash bank1 */
|
||||
address = BANK1_WRITE_START_ADDR;
|
||||
wperror2 = 0;
|
||||
while(address < BANK1_WRITE_END_ADDR){
|
||||
fmcstatus = fmc_word_program(address, transdata);
|
||||
address = address + 4;
|
||||
wperror2 += (FMC_WPERR == fmcstatus);
|
||||
fmc_flag_clear(FMC_FLAG_PGERR | FMC_FLAG_WPERR | FMC_FLAG_END);
|
||||
}
|
||||
|
||||
fmc_lock();
|
||||
|
||||
/* DMA channel0 initialize */
|
||||
dma_deinit(DMA_CH0);
|
||||
dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
|
||||
dma_init_struct.memory_addr = (uint32_t)destdata;
|
||||
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
|
||||
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
|
||||
dma_init_struct.number = ACCESSSUM;
|
||||
dma_init_struct.periph_addr = (uint32_t)BANK1_WRITE_START_ADDR;
|
||||
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_ENABLE;
|
||||
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
|
||||
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
|
||||
dma_init(DMA_CH0,dma_init_struct);
|
||||
/* DMA channel0 mode configuration */
|
||||
dma_circulation_disable(DMA_CH0);
|
||||
dma_memory_to_memory_enable(DMA_CH0);
|
||||
/* DMA channel0 interrupt configuration */
|
||||
dma_interrupt_enable(DMA_CH0, DMA_INT_FTF);
|
||||
/* enable DMA transfer */
|
||||
dma_channel_enable(DMA_CH0);
|
||||
|
||||
/* wait DMA interrupt */
|
||||
for(i = 0; i < 10000; i++){
|
||||
if(int_num)
|
||||
break;
|
||||
}
|
||||
|
||||
/* compare destdata with transdata */
|
||||
ptrd = destdata;
|
||||
for(i = 0; i < 256; i++){
|
||||
if(transdata != *ptrd)
|
||||
{
|
||||
accessflag = ERROR;
|
||||
break;
|
||||
}
|
||||
ptrd++;
|
||||
}
|
||||
|
||||
/* transfer sucess */
|
||||
if(accessflag != ERROR){
|
||||
gd_eval_led_off(LED1);
|
||||
gd_eval_led_off(LED3);
|
||||
gd_eval_led_on(LED2);
|
||||
gd_eval_led_on(LED4);
|
||||
}else{
|
||||
/* transfer fail */
|
||||
gd_eval_led_off(LED2);
|
||||
gd_eval_led_off(LED4);
|
||||
gd_eval_led_on(LED1);
|
||||
gd_eval_led_on(LED3);
|
||||
}
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure LED
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void led_config(void)
|
||||
{
|
||||
gd_eval_led_init (LED1);
|
||||
gd_eval_led_init (LED2);
|
||||
gd_eval_led_init (LED3);
|
||||
gd_eval_led_init (LED4);
|
||||
|
||||
/* LED off */
|
||||
gd_eval_led_off(LED1);
|
||||
gd_eval_led_off(LED3);
|
||||
gd_eval_led_off(LED2);
|
||||
gd_eval_led_off(LED4);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the different system clocks
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void rcu_config(void)
|
||||
{
|
||||
/* enable DMA clock */
|
||||
rcu_periph_clock_enable(RCU_DMA);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the nested vectored interrupt controller
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_config(void)
|
||||
{
|
||||
nvic_irq_enable(DMA_Channel0_IRQn,0,0);
|
||||
}
|
||||
|
||||
@@ -0,0 +1,28 @@
|
||||
/*!
|
||||
\file readme.txt
|
||||
\brief description of the DMA flash to ram example
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2017 GigaDevice
|
||||
|
||||
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
|
||||
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
|
||||
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
*/
|
||||
|
||||
This example is based on the GD32150R-EVAL/ GD32190R-EVAL board, it provides a description
|
||||
of how to use DMA channel0 to transfer data buffer from FLASH memory to embedded SRAM memory.
|
||||
|
||||
Before programming the flash addresses, an erase operation is performed firstly.
|
||||
After the erase operation, a comparison between FLASH memory and 0xFFFFFFFF(Reset value)
|
||||
is done to check that the FLASH memory has been correctly erased.
|
||||
|
||||
Once the erase operation is finished correctly, the programming operation will be
|
||||
performed by using the fmc_programword function. The written data is transfered to
|
||||
embedded SRAM memory by DMA1 Channel1. The transfer is started by enabling the DMA1 Channel1.
|
||||
At the end of the transfer, a Transfer Complete interrupt is generated since it
|
||||
is enabled. A comparison between the FLASH memory and embedded SRAM memory is done to
|
||||
check that all data have been correctly transferred.If the result of comparison is passed,
|
||||
LED2 and LED4 light up. Otherwise LED1 and LED3 light up.
|
||||
@@ -0,0 +1,47 @@
|
||||
/*!
|
||||
\file gd32f1x0_libopt.h
|
||||
\brief library optional for gd32f1x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2017 GigaDevice
|
||||
|
||||
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
|
||||
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
|
||||
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
*/
|
||||
|
||||
#ifndef GD32F1X0_LIBOPT_H
|
||||
#define GD32F1X0_LIBOPT_H
|
||||
|
||||
#include "gd32f1x0_adc.h"
|
||||
#include "gd32f1x0_cec.h"
|
||||
#include "gd32f1x0_crc.h"
|
||||
#include "gd32f1x0_cmp.h"
|
||||
#include "gd32f1x0_dac.h"
|
||||
#include "gd32f1x0_dbg.h"
|
||||
#include "gd32f1x0_dma.h"
|
||||
#include "gd32f1x0_exti.h"
|
||||
#include "gd32f1x0_fmc.h"
|
||||
#include "gd32f1x0_gpio.h"
|
||||
#include "gd32f1x0_syscfg.h"
|
||||
#include "gd32f1x0_i2c.h"
|
||||
#include "gd32f1x0_fwdgt.h"
|
||||
#include "gd32f1x0_pmu.h"
|
||||
#include "gd32f1x0_rcu.h"
|
||||
#include "gd32f1x0_rtc.h"
|
||||
#include "gd32f1x0_spi.h"
|
||||
#include "gd32f1x0_timer.h"
|
||||
#include "gd32f1x0_usart.h"
|
||||
#include "gd32f1x0_wwdgt.h"
|
||||
#include "gd32f1x0_misc.h"
|
||||
#include "gd32f1x0_tsi.h"
|
||||
#ifdef GD32F170_190
|
||||
#include "gd32f1x0_slcd.h"
|
||||
#include "gd32f1x0_opa.h"
|
||||
#include "gd32f1x0_ivref.h"
|
||||
#include "gd32f1x0_can.h"
|
||||
#endif /* GD32F170_190 */
|
||||
|
||||
#endif /* GD32F1X0_LIBOPT_H */
|
||||
@@ -0,0 +1,157 @@
|
||||
/*!
|
||||
\file main.c
|
||||
\brief transfer data from RAM to RAM
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2017 GigaDevice
|
||||
|
||||
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
|
||||
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
|
||||
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
*/
|
||||
|
||||
#include "gd32f1x0.h"
|
||||
#include "gd32f1x0_eval.h"
|
||||
|
||||
#define DATANUM 16
|
||||
|
||||
__IO ErrStatus transferflag1 = ERROR;
|
||||
__IO ErrStatus transferflag2 = ERROR;
|
||||
__IO ErrStatus transferflag3 = ERROR;
|
||||
__IO ErrStatus transferflag4 = ERROR;
|
||||
uint8_t source_address[DATANUM]= {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,
|
||||
0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10};
|
||||
uint8_t destination_address1[DATANUM];
|
||||
uint8_t destination_address2[DATANUM];
|
||||
uint8_t destination_address3[DATANUM];
|
||||
uint8_t destination_address4[DATANUM];
|
||||
|
||||
void led_config(void);
|
||||
ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length);
|
||||
|
||||
/*!
|
||||
\brief main function
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
int i = 0;
|
||||
dma_parameter_struct dma_init_struct;
|
||||
/* enable DMA clock */
|
||||
rcu_periph_clock_enable(RCU_DMA);
|
||||
/* initialize LED */
|
||||
led_config();
|
||||
/* all LED off */
|
||||
gd_eval_led_off(LED1);
|
||||
gd_eval_led_off(LED3);
|
||||
gd_eval_led_off(LED2);
|
||||
gd_eval_led_off(LED4);
|
||||
/* initialize DMA channel1 */
|
||||
dma_deinit(DMA_CH1);
|
||||
dma_init_struct.direction = DMA_PERIPHERAL_TO_MEMORY;
|
||||
dma_init_struct.memory_addr = (uint32_t)destination_address1;
|
||||
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
|
||||
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
|
||||
dma_init_struct.number = DATANUM;
|
||||
dma_init_struct.periph_addr = (uint32_t)source_address;
|
||||
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_ENABLE;
|
||||
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
|
||||
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
|
||||
dma_init(DMA_CH1,dma_init_struct);
|
||||
/* configure DMA mode */
|
||||
dma_circulation_disable(DMA_CH1);
|
||||
dma_memory_to_memory_enable(DMA_CH1);
|
||||
|
||||
/* initialize DMA channel2 */
|
||||
dma_deinit(DMA_CH2);
|
||||
dma_init_struct.memory_addr = (uint32_t)destination_address2;
|
||||
dma_init(DMA_CH2,dma_init_struct);
|
||||
/* configure DMA mode */
|
||||
dma_circulation_disable(DMA_CH2);
|
||||
dma_memory_to_memory_enable(DMA_CH2);
|
||||
|
||||
/* initialize DMA channel3 */
|
||||
dma_deinit(DMA_CH3);
|
||||
dma_init_struct.memory_addr = (uint32_t)destination_address3;
|
||||
dma_init(DMA_CH3,dma_init_struct);
|
||||
/* configure DMA mode */
|
||||
dma_circulation_disable(DMA_CH3);
|
||||
dma_memory_to_memory_enable(DMA_CH3);
|
||||
|
||||
/* initialize DMA channel4 */
|
||||
dma_deinit(DMA_CH4);
|
||||
dma_init_struct.memory_addr = (uint32_t)destination_address4;
|
||||
dma_init(DMA_CH4,dma_init_struct);
|
||||
/* configure DMA mode */
|
||||
dma_circulation_disable(DMA_CH4);
|
||||
dma_memory_to_memory_enable(DMA_CH4);
|
||||
|
||||
/* enable DMA channel1~channel4 */
|
||||
dma_channel_enable(DMA_CH1);
|
||||
dma_channel_enable(DMA_CH2);
|
||||
dma_channel_enable(DMA_CH3);
|
||||
dma_channel_enable(DMA_CH4);
|
||||
|
||||
/* wait for DMA transfer complete */
|
||||
for(i = 0; i < 200; i++);
|
||||
/* compare the data of source_address with data of destination_address */
|
||||
transferflag1 = memory_compare(source_address, destination_address1, DATANUM);
|
||||
transferflag2 = memory_compare(source_address, destination_address2, DATANUM);
|
||||
transferflag3 = memory_compare(source_address, destination_address3, DATANUM);
|
||||
transferflag4 = memory_compare(source_address, destination_address4, DATANUM);
|
||||
|
||||
/* if DMA channel1 transfer success,light LED1 */
|
||||
if(SUCCESS == transferflag1){
|
||||
gd_eval_led_on(LED1);
|
||||
}
|
||||
/* if DMA channel2 transfer success,light LED2 */
|
||||
if(SUCCESS == transferflag2){
|
||||
gd_eval_led_on(LED2);
|
||||
}
|
||||
/* if DMA channel3 transfer success,light LED3 */
|
||||
if(SUCCESS == transferflag3){
|
||||
gd_eval_led_on(LED3);
|
||||
}
|
||||
/* if DMA channel4 transfer success,light LED4 */
|
||||
if(SUCCESS == transferflag4){
|
||||
gd_eval_led_on(LED4);
|
||||
}
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief LEDs configure
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void led_config(void)
|
||||
{
|
||||
gd_eval_led_init (LED1);
|
||||
gd_eval_led_init (LED2);
|
||||
gd_eval_led_init (LED3);
|
||||
gd_eval_led_init (LED4);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief memory compare function
|
||||
\param[in] src : source data
|
||||
\param[in] dst : destination data
|
||||
\param[in] length : the compare data length
|
||||
\param[out] none
|
||||
\retval ErrStatus : ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus memory_compare(uint8_t* src, uint8_t* dst, uint16_t length)
|
||||
{
|
||||
while (length--){
|
||||
if (*src++ != *dst++){
|
||||
return ERROR;
|
||||
}
|
||||
}
|
||||
return SUCCESS;
|
||||
}
|
||||
@@ -0,0 +1,23 @@
|
||||
/*!
|
||||
\file readme.txt
|
||||
\brief description of DMA ram to ram
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2017 GigaDevice
|
||||
|
||||
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
|
||||
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
|
||||
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
*/
|
||||
|
||||
This example is based on the GD32150R-EVAL/ GD32190R-EVAL board, it provides a description
|
||||
of how to use DMA channel(1 to 4) to transfer data from RAM to RAM.DMA Channel(1 to 4) is
|
||||
configured to transfer the contents of data buffer stored in "source_address" to the
|
||||
reception buffer declared in RAM(destination_address1~destination_address4).
|
||||
|
||||
The start of transfer is triggered by software. At the end of the transfer, a comparison
|
||||
between the source and destination buffers is done to check that all data have been correctly
|
||||
transferred.If transfer correctly the corresponding LED light.If transfer do not correcly,the
|
||||
corresponding LED is off.
|
||||
@@ -0,0 +1,149 @@
|
||||
/*!
|
||||
\file gd32f1x0_it.c
|
||||
\brief interrupt service routines
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2017 GigaDevice
|
||||
|
||||
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
|
||||
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
|
||||
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
*/
|
||||
|
||||
#include "gd32f1x0_it.h"
|
||||
|
||||
extern __IO uint32_t transfer;
|
||||
|
||||
/*!
|
||||
\brief this function handles NMI exception
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief this function handles HardFault exception
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
/* if Hard Fault exception occurs, go to infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief this function handles MemManage exception
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void MemManage_Handler(void)
|
||||
{
|
||||
/* if Memory Manage exception occurs, go to infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief this function handles BusFault exception
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void BusFault_Handler(void)
|
||||
{
|
||||
/* if Bus Fault exception occurs, go to infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief this function handles UsageFault exception
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void UsageFault_Handler(void)
|
||||
{
|
||||
/* if Usage Fault exception occurs, go to infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief this function handles SVC exception
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void SVC_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief this function handles DebugMon exception
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void DebugMon_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief this function handles PendSV exception
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void PendSV_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief this function handles SysTick exception
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
#ifdef GD32F130_150
|
||||
|
||||
/*!
|
||||
\brief this function handles DMA_Channel1_2_IRQHandler interrupt
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void DMA_Channel1_2_IRQHandler(void)
|
||||
{
|
||||
if(dma_interrupt_flag_get(DMA_CH1, DMA_INT_FLAG_FTF)){
|
||||
transfer++;
|
||||
dma_interrupt_flag_clear(DMA_CH1, DMA_INT_FLAG_G);
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined GD32F170_190
|
||||
|
||||
/*!
|
||||
\brief this function handles DMA_Channel3_4_IRQHandler interrupt
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void DMA_Channel3_4_IRQHandler(void)
|
||||
{
|
||||
if(dma_interrupt_flag_get(DMA_CH3, DMA_INT_FLAG_FTF)){
|
||||
transfer++;
|
||||
dma_interrupt_flag_clear(DMA_CH3, DMA_INT_FLAG_G);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* GD32F130_150 */
|
||||
@@ -0,0 +1,52 @@
|
||||
/*!
|
||||
\file gd32f1x0_it.h
|
||||
\brief the header file of the ISR
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2017 GigaDevice
|
||||
|
||||
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
|
||||
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
|
||||
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
*/
|
||||
|
||||
#ifndef GD32F1X0_IT_H
|
||||
#define GD32F1X0_IT_H
|
||||
|
||||
#include "gd32f1x0.h"
|
||||
|
||||
/* function declarations */
|
||||
/* NMI handle function */
|
||||
void NMI_Handler(void);
|
||||
/* HardFault handle function */
|
||||
void HardFault_Handler(void);
|
||||
/* MemManage handle function */
|
||||
void MemManage_Handler(void);
|
||||
/* BusFault handle function */
|
||||
void BusFault_Handler(void);
|
||||
/* UsageFault handle function */
|
||||
void UsageFault_Handler(void);
|
||||
/* SVC handle function */
|
||||
void SVC_Handler(void);
|
||||
/* DebugMon handle function */
|
||||
void DebugMon_Handler(void);
|
||||
/* PendSV handle function */
|
||||
void PendSV_Handler(void);
|
||||
/* SysTick handle function */
|
||||
void SysTick_Handler(void);
|
||||
|
||||
#ifdef GD32F130_150
|
||||
|
||||
/* DMA_Channel1_2 handle function */
|
||||
void DMA_Channel1_2_IRQHandler(void);
|
||||
|
||||
#elif defined GD32F170_190
|
||||
|
||||
/* DMA_Channel3_4 handle function */
|
||||
void DMA_Channel3_4_IRQHandler(void);
|
||||
|
||||
#endif /* GD32F130_150 */
|
||||
|
||||
#endif /* GD32F1X0_IT_H */
|
||||
@@ -0,0 +1,47 @@
|
||||
/*!
|
||||
\file gd32f1x0_libopt.h
|
||||
\brief library optional for gd32f1x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2017 GigaDevice
|
||||
|
||||
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
|
||||
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
|
||||
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
*/
|
||||
|
||||
#ifndef GD32F1X0_LIBOPT_H
|
||||
#define GD32F1X0_LIBOPT_H
|
||||
|
||||
#include "gd32f1x0_adc.h"
|
||||
#include "gd32f1x0_cec.h"
|
||||
#include "gd32f1x0_crc.h"
|
||||
#include "gd32f1x0_cmp.h"
|
||||
#include "gd32f1x0_dac.h"
|
||||
#include "gd32f1x0_dbg.h"
|
||||
#include "gd32f1x0_dma.h"
|
||||
#include "gd32f1x0_exti.h"
|
||||
#include "gd32f1x0_fmc.h"
|
||||
#include "gd32f1x0_gpio.h"
|
||||
#include "gd32f1x0_syscfg.h"
|
||||
#include "gd32f1x0_i2c.h"
|
||||
#include "gd32f1x0_fwdgt.h"
|
||||
#include "gd32f1x0_pmu.h"
|
||||
#include "gd32f1x0_rcu.h"
|
||||
#include "gd32f1x0_rtc.h"
|
||||
#include "gd32f1x0_spi.h"
|
||||
#include "gd32f1x0_timer.h"
|
||||
#include "gd32f1x0_usart.h"
|
||||
#include "gd32f1x0_wwdgt.h"
|
||||
#include "gd32f1x0_misc.h"
|
||||
#include "gd32f1x0_tsi.h"
|
||||
#ifdef GD32F170_190
|
||||
#include "gd32f1x0_slcd.h"
|
||||
#include "gd32f1x0_opa.h"
|
||||
#include "gd32f1x0_ivref.h"
|
||||
#include "gd32f1x0_can.h"
|
||||
#endif /* GD32F170_190 */
|
||||
|
||||
#endif /* GD32F1X0_LIBOPT_H */
|
||||
@@ -0,0 +1,146 @@
|
||||
/*!
|
||||
\file main.c
|
||||
\brief transfer data from RAM to USART
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2017 GigaDevice
|
||||
|
||||
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
|
||||
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
|
||||
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
*/
|
||||
|
||||
#include "gd32f1x0.h"
|
||||
#include "gd32f1x0_eval.h"
|
||||
|
||||
#define USART0_DATA_ADDRESS ((uint32_t)0x40013828) /* 130_150 device */
|
||||
#define USART1_DATA_ADDRESS ((uint32_t)0x40004428) /* 170_190 device */
|
||||
#define ARRAYNUM(arr_nanme) (uint32_t)(sizeof(arr_nanme) / sizeof(*(arr_nanme)))
|
||||
|
||||
uint8_t welcome[]="hi,this is a example: RAM_TO_USART by DMA !\n";
|
||||
__IO uint32_t transfer;
|
||||
|
||||
void led_config(void);
|
||||
void nvic_config(void);
|
||||
|
||||
/*!
|
||||
\brief main function
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
dma_parameter_struct dma_init_struct;
|
||||
/* enable DMA clock */
|
||||
rcu_periph_clock_enable(RCU_DMA);
|
||||
|
||||
/* initialize LED */
|
||||
led_config();
|
||||
|
||||
/* all LED off */
|
||||
gd_eval_led_off(LED1);
|
||||
|
||||
/*configure DMA interrupt*/
|
||||
nvic_config();
|
||||
|
||||
#ifdef GD32F130_150
|
||||
|
||||
/* USART configure */
|
||||
gd_eval_com_init(EVAL_COM1);
|
||||
|
||||
/* initialize DMA channel1 */
|
||||
dma_deinit(DMA_CH1);
|
||||
dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
|
||||
dma_init_struct.memory_addr = (uint32_t)welcome;
|
||||
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
|
||||
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
|
||||
dma_init_struct.number = ARRAYNUM(welcome);
|
||||
dma_init_struct.periph_addr = USART0_DATA_ADDRESS;
|
||||
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
|
||||
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
|
||||
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
|
||||
dma_init(DMA_CH1,dma_init_struct);
|
||||
|
||||
/* configure DMA mode */
|
||||
dma_circulation_disable(DMA_CH1);
|
||||
dma_memory_to_memory_disable(DMA_CH1);
|
||||
|
||||
/* USART DMA enable for transmission */
|
||||
usart_dma_transmit_config(USART0,USART_DENT_ENABLE);
|
||||
|
||||
/* enable DMA transfer complete interrupt */
|
||||
dma_interrupt_enable(DMA_CH1,DMA_CHXCTL_FTFIE);
|
||||
|
||||
/* enable DMA channel1 */
|
||||
dma_channel_enable(DMA_CH1);
|
||||
|
||||
#elif defined GD32F170_190
|
||||
|
||||
/* USART configure */
|
||||
gd_eval_COMinit(EVAL_COM2);
|
||||
|
||||
/* initialize DMA channel3 */
|
||||
dma_deinit(DMA_CH3);
|
||||
dma_init_struct.direction = DMA_MEMORY_TO_PERIPHERAL;
|
||||
dma_init_struct.memory_addr = (uint32_t)welcome;
|
||||
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
|
||||
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
|
||||
dma_init_struct.number = ARRAYNUM(welcome);
|
||||
dma_init_struct.periph_addr = USART1_DATA_ADDRESS;
|
||||
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
|
||||
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
|
||||
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
|
||||
dma_init(DMA_CH3,dma_init_struct);
|
||||
|
||||
/* configure DMA mode */
|
||||
dma_circulation_disable(DMA_CH3);
|
||||
dma_memory_to_memory_disable(DMA_CH3);
|
||||
|
||||
/* USART DMA enable for transmission */
|
||||
usart_dma_transfer_config(USART1,USART_DENT_ENABLE);
|
||||
|
||||
/* enable DMA transfer complete interrupt */
|
||||
dma_interrupt_enable(DMA_CH3,DMA_INT_FTF);
|
||||
|
||||
/* enable DMA channel3 */
|
||||
dma_channel_enable(DMA_CH3);
|
||||
|
||||
#endif /* GD32F130_150 */
|
||||
|
||||
/* waiting for the transfer to complete*/
|
||||
while(0 == transfer);
|
||||
|
||||
/* light LED1 */
|
||||
gd_eval_led_on(LED1);
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief LEDs configure
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void led_config(void)
|
||||
{
|
||||
gd_eval_led_init (LED1);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure DMA interrupt
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_config(void)
|
||||
{
|
||||
#ifdef GD32F130_150
|
||||
nvic_irq_enable(DMA_Channel1_2_IRQn,0,0);
|
||||
#elif defined GD32F170_190
|
||||
nvic_irq_enable(DMA_Channel3_4_IRQn,0,0);
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,20 @@
|
||||
/*!
|
||||
\file readme.txt
|
||||
\brief description of DMA ram to usart
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2017 GigaDevice
|
||||
|
||||
2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
|
||||
2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
|
||||
2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
|
||||
*/
|
||||
|
||||
This example is based on the GD32150R-EVAL/ GD32190R-EVAL board, it provides a description
|
||||
of how to use DMA channel1/ channel3 to transfer data from RAM memory to USART transmit data
|
||||
register.The start of transfer is triggered by software. At the end of the transfer, a
|
||||
transfer complete interrupt is generated since it is enabled. If the DMA transfer
|
||||
operation is finished correctly, data stored array welcome[] will be transfered
|
||||
to a serial port tool by USART and LED1 light up.
|
||||
Reference in New Issue
Block a user