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244 lines
10 KiB
C
244 lines
10 KiB
C
/*!
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\file gd32f1x0_dac.h
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\brief definitions for the DAC
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*/
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/*
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Copyright (C) 2017 GigaDevice
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2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
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2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
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2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
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2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
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*/
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#ifndef GD32F1X0_DAC_H
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#define GD32F1X0_DAC_H
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#include "gd32f1x0.h"
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/* DACx(x=0,1) definitions */
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#define DAC DAC_BASE
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#define DAC0 0U
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#ifdef GD32F170_190
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#define DAC1 1U
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#endif /* GD32F170_190 */
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/* registers definitions */
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#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */
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#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */
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#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */
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#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */
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#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */
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#ifdef GD32F170_190
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#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */
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#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */
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#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */
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#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */
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#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */
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#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */
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#endif /* GD32F170_190 */
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#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 output data register */
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#ifdef GD32F170_190
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#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 output data register */
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#endif /* GD32F170_190 */
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#define DAC_STAT REG32(DAC + 0x34U) /*!< DAC status register */
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/* bits definitions */
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/* DAC_CTL */
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#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */
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#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */
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#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */
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#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */
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#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disanle bit */
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#define DAC_CTL_DDUDRIE0 BIT(13) /*!< DAC0 DMA underrun Interrupt enable/disable bit */
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#ifdef GD32F170_190
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#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */
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#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */
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#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */
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#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */
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#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */
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#define DAC_CTL_DDUDRIE1 BIT(29) /*!< DAC1 DMA underrun interrupt enable/disable bit */
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#endif /* GD32F170_190 */
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/* DAC_SWT */
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#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit,cleared by hardware */
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#ifdef GD32F170_190
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#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit,cleared by hardware */
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#endif /* GD32F170_190 */
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/* DAC0_R12DH */
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#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */
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/* DAC0_L12DH */
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#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */
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/* DAC0_R8DH */
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#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */
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#ifdef GD32F170_190
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/* DAC1_R12DH */
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#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */
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/* DAC1_L12DH */
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#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */
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/* DAC1_R8DH */
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#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */
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/* DACC_R12DH */
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#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */
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#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */
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/* DACC_L12DH */
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#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */
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#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */
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/* DACC_R8DH */
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#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */
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#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */
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#endif /* GD32F170_190 */
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/* DAC0_DO */
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#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */
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#ifdef GD32F170_190
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/* DAC1_DO */
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#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */
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#endif /* GD32F170_190 */
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/* DAC_STAT */
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#define DAC_STAT_DDUDR0 BIT(13) /*!< DAC0 DMA underrun flag */
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#ifdef GD32F170_190
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#define DAC_STAT_DDUDR1 BIT(29) /*!< DAC1 DMA underrun flag */
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#endif /* GD32F170_190 */
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/* constants definitions */
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/* DAC trigger source */
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#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
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#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */
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#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */
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#define DAC_TRIGGER_T14_TRGO CTL_DTSEL(3) /*!< TIMER14 TRGO */
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#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */
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#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */
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#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */
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/* dac data alignment */
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#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
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#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */
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#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */
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#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */
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/* function declarations */
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/* deinit DAC */
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void dac_deinit(void);
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/* enable DAC0 function */
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void dac0_enable(void);
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/* disable DAC0 function */
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void dac0_disable(void);
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/* enable DAC0 DMA function */
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void dac0_dma_enable(void);
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/* disable DAC0 DMA function */
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void dac0_dma_disable(void);
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/* enable DAC0 output buffer function */
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void dac0_output_buffer_enable(void);
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/* disable DAC0 output buffer function */
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void dac0_output_buffer_disable(void);
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/* enable DAC0 trigger function */
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void dac0_trigger_enable(void);
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/* disable DAC0 trigger function */
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void dac0_trigger_disable(void);
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/* enable DAC0 software trigger function */
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void dac0_software_trigger_enable(void);
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/* disable DAC0 software trigger function */
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void dac0_software_trigger_disable(void);
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/* enable DAC0 interrupt(DAC0 DMA underrun interrupt) */
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void dac0_interrupt_enable(void);
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/* disable DAC0 interrupt(DAC0 DMA underrun interrupt) */
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void dac0_interrupt_disable(void);
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/* set DAC0 tgigger source function */
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void dac0_trigger_source_config(uint32_t triggersource);
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/* get the last data output value */
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uint16_t dac0_output_value_get(void);
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/* get the specified DAC0 flag(DAC0 DMA underrun flag) */
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FlagStatus dac0_flag_get(void);
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/* clear the specified DAC0 flag(DAC0 DMA underrun flag) */
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void dac0_flag_clear(void);
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/* get the specified DAC0 interrupt flag(DAC0 DMA underrun interrupt flag) */
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FlagStatus dac0_interrupt_flag_get(void);
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/* clear the specified DAC0 interrupt flag(DAC0 DMA underrun interrupt flag) */
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void dac0_interrupt_flag_clear(void);
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/* set DAC0 data holding register value */
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void dac0_data_set(uint32_t dac_align, uint16_t data);
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#ifdef GD32F170_190
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/* enable DAC */
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void dac_enable(uint32_t dac_periph);
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/* disable DAC */
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void dac_disable(uint32_t dac_periph);
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/* enable DAC DMA */
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void dac_dma_enable(uint32_t dac_periph);
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/* disable DAC DMA */
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void dac_dma_disable(uint32_t dac_periph);
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/* enable DAC output buffer */
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void dac_output_buffer_enable(uint32_t dac_periph);
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/* disable DAC output buffer */
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void dac_output_buffer_disable(uint32_t dac_periph);
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/* enable DAC trigger */
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void dac_trigger_enable(uint32_t dac_periph);
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/* disable DAC trigger */
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void dac_trigger_disable(uint32_t dac_periph);
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/* enable DAC software trigger */
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void dac_software_trigger_enable(uint32_t dac_periph);
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/* disable DAC software trigger */
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void dac_software_trigger_disable(uint32_t dac_periph);
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/* enable DAC interrupt(DAC0 DMA underrun interrupt) */
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void dac_interrupt_enable(uint32_t dac_periph);
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/* disable DAC interrupt(DAC0 DMA underrun interrupt) */
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void dac_interrupt_disable(uint32_t dac_periph);
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/* set DAC tgigger source */
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void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource);
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/* get the last data output value */
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uint16_t dac_output_value_get(uint32_t dac_periph);
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/* get the specified DAC flag(DAC DMA underrun flag) */
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FlagStatus dac_flag_get(uint32_t dac_periph);
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/* clear the specified DAC flag(DAC DMA underrun flag) */
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void dac_flag_clear(uint32_t dac_periph);
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/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
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FlagStatus dac_interrupt_flag_get(uint32_t dac_periph);
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/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
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void dac_interrupt_flag_clear(uint32_t dac_periph);
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/* enable DAC concurrent mode */
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void dac_concurrent_enable(void);
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/* disable DAC concurrent mode */
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void dac_concurrent_disable(void);
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/* enable DAC concurrent software trigger */
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void dac_concurrent_software_trigger_enable(void);
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/* disable DAC concurrent software trigger */
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void dac_concurrent_software_trigger_disable(void);
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/* enable DAC concurrent buffer */
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void dac_concurrent_output_buffer_enable(void);
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/* disable DAC concurrent buffer */
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void dac_concurrent_output_buffer_disable(void);
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/* enable DAC concurrent interrupt */
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void dac_concurrent_interrupt_enable(void);
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/* disable DAC concurrent interrupt */
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void dac_concurrent_interrupt_disable(void);
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/* set DAC data holding register value */
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void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data);
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/* set DAC concurrent mode data holding register value */
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void dac_concurrent_data_set(uint32_t dac_align, uint16_t data1, uint16_t data2);
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#endif /* GD32F170_190 */
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#endif /* GD32F1X0_DAC_H */
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