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72 lines
3.1 KiB
C
72 lines
3.1 KiB
C
/*!
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\file gd32f1x0_misc.h
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\brief definitions for the MISC
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*/
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/*
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Copyright (C) 2017 GigaDevice
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2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
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2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
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2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
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2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
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*/
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#ifndef GD32F1X0_MISC_H
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#define GD32F1X0_MISC_H
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#include "gd32f1x0.h"
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/* constants definitions */
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/* set the RAM and FLASH base address */
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#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000U) /*!< RAM base address */
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#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000U) /*!< Flash base address */
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/* set the NVIC vector table offset mask */
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#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80U)
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/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
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#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000U)
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/* priority group - define the pre-emption priority and the subpriority */
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#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700U) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
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#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600U) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
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#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500U) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
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#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400U) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
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#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300U) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
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/* choose the method to enter or exit the lowpower mode */
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#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02U) /*!< choose the the system whether enter low power mode by exiting from ISR */
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#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04U) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
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#define SCB_SCR_SEVONPEND ((uint8_t)0x10U) /*!< choose the interrupt source that can wake up the lowpower mode */
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#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT
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#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP
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#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND
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/* choose the systick clock source */
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#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
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#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
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/* function declarations */
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/* set the priority group */
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void nvic_priority_group_set(uint32_t nvic_prigroup);
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/* enable NVIC request */
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void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
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/* disable NVIC request */
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void nvic_irq_disable(uint8_t nvic_irq);
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/* set the NVIC vector table base address */
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void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
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/* set the state of the low power mode */
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void system_lowpower_set(uint8_t lowpower_mode);
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/* reset the state of the low power mode */
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void system_lowpower_reset(uint8_t lowpower_mode);
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/* set the systick clock source */
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void systick_clksource_set(uint32_t systick_clksource);
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#endif /* GD32F1X0_MISC_H */
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