mirror of
https://github.com/EFeru/hoverboard-sideboard-hack-GD.git
synced 2025-07-27 17:49:32 +00:00
329 lines
14 KiB
ArmAsm
329 lines
14 KiB
ArmAsm
;/*!
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; \file startup_gd32f1x0.s
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; \brief start up file
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;*/
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;/*
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; Copyright (C) 2017 GigaDevice
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; 2014-12-26, V1.0.0, firmware for GD32F1x0(x=3,5)
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; 2016-01-15, V2.0.0, firmware for GD32F1x0(x=3,5,7,9)
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; 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
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; 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
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;*/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000400
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; /* reset Vector Mapped to at Address 0 */
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; /* external interrupts handler */
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DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
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DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
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DCD RTC_IRQHandler ; 18:RTC through EXTI Line
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DCD FMC_IRQHandler ; 19:FMC
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DCD RCU_IRQHandler ; 20:RCU
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DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1
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DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3
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DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15
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DCD TSI_IRQHandler ; 24:TSI
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DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0
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DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2
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DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4
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DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator 0-1
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DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation
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DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel
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DCD TIMER1_IRQHandler ; 31:TIMER1
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DCD TIMER2_IRQHandler ; 32:TIMER2
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DCD TIMER5_DAC_IRQHandler ; 33:TIMER5 and DAC
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DCD 0 ; Reserved
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DCD TIMER13_IRQHandler ; 35:TIMER13
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DCD TIMER14_IRQHandler ; 36:TIMER14
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DCD TIMER15_IRQHandler ; 37:TIMER15
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DCD TIMER16_IRQHandler ; 38:TIMER16
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DCD I2C0_EV_IRQHandler ; 39:I2C0 Event
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DCD I2C1_EV_IRQHandler ; 40:I2C1 Event
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DCD SPI0_IRQHandler ; 41:SPI0
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DCD SPI1_IRQHandler ; 42:SPI1
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DCD USART0_IRQHandler ; 43:USART0
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DCD USART1_IRQHandler ; 44:USART1
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DCD 0 ; Reserved
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DCD CEC_IRQHandler ; 46:CEC
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DCD 0 ; Reserved
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DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
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DCD 0 ; Reserved
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DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
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DCD I2C2_EV_IRQHandler ; 51:I2C2 Event
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DCD I2C2_ER_IRQHandler ; 52:I2C2 Error
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DCD USBD_LP_IRQHandler ; 53:USBD LP
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DCD USBD_HP_IRQHandler ; 54:USBD HP
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD USBDWakeUp_IRQHandler ; 58:USBD Wakeup
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DCD CAN0_TX_IRQHandler ; 59:CAN0 TX
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DCD CAN0_RX0_IRQHandler ; 60:CAN0 RX0
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DCD CAN0_RX1_IRQHandler ; 61:CAN0 RX1
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DCD CAN0_SCE_IRQHandler ; 62:CAN0 SCE
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DCD SLCD_IRQHandler ; 63:SLCD
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DCD DMA_Channel5_6_IRQHandler ; 64:DMA Channel5 and Channel6
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SPI2_IRQHandler ; 67:SPI2
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD CAN1_TX_IRQHandler ; 86:CAN1 TX
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DCD CAN1_RX0_IRQHandler ; 87:CAN1 RX0
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DCD CAN1_RX1_IRQHandler ; 88:CAN1 RX1
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DCD CAN1_SCE_IRQHandler ; 89:CAN1 SCE
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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;/* reset Handler */
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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;/* dummy Exception Handlers */
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler\
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PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler\
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PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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; /* external interrupts handler */
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EXPORT WWDGT_IRQHandler [WEAK]
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EXPORT LVD_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT FMC_IRQHandler [WEAK]
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EXPORT RCU_IRQHandler [WEAK]
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EXPORT EXTI0_1_IRQHandler [WEAK]
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EXPORT EXTI2_3_IRQHandler [WEAK]
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EXPORT EXTI4_15_IRQHandler [WEAK]
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EXPORT TSI_IRQHandler [WEAK]
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EXPORT DMA_Channel0_IRQHandler [WEAK]
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EXPORT DMA_Channel1_2_IRQHandler [WEAK]
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EXPORT DMA_Channel3_4_IRQHandler [WEAK]
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EXPORT ADC_CMP_IRQHandler [WEAK]
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EXPORT TIMER0_BRK_UP_TRG_COM_IRQHandler [WEAK]
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EXPORT TIMER0_Channel_IRQHandler [WEAK]
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EXPORT TIMER1_IRQHandler [WEAK]
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EXPORT TIMER2_IRQHandler [WEAK]
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EXPORT TIMER5_DAC_IRQHandler [WEAK]
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EXPORT TIMER13_IRQHandler [WEAK]
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EXPORT TIMER14_IRQHandler [WEAK]
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EXPORT TIMER15_IRQHandler [WEAK]
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EXPORT TIMER16_IRQHandler [WEAK]
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EXPORT I2C0_EV_IRQHandler [WEAK]
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EXPORT I2C1_EV_IRQHandler [WEAK]
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EXPORT SPI0_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT USART0_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT CEC_IRQHandler [WEAK]
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EXPORT I2C0_ER_IRQHandler [WEAK]
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EXPORT I2C1_ER_IRQHandler [WEAK]
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EXPORT I2C2_EV_IRQHandler [WEAK]
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EXPORT I2C2_ER_IRQHandler [WEAK]
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EXPORT USBD_LP_IRQHandler [WEAK]
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EXPORT USBD_HP_IRQHandler [WEAK]
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EXPORT USBDWakeUp_IRQHandler [WEAK]
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EXPORT CAN0_TX_IRQHandler [WEAK]
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EXPORT CAN0_RX0_IRQHandler [WEAK]
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EXPORT CAN0_RX1_IRQHandler [WEAK]
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EXPORT CAN0_SCE_IRQHandler [WEAK]
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EXPORT SLCD_IRQHandler [WEAK]
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EXPORT DMA_Channel5_6_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT CAN1_TX_IRQHandler [WEAK]
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EXPORT CAN1_RX0_IRQHandler [WEAK]
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EXPORT CAN1_RX1_IRQHandler [WEAK]
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EXPORT CAN1_SCE_IRQHandler [WEAK]
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;/* external interrupts handler */
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WWDGT_IRQHandler
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LVD_IRQHandler
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RTC_IRQHandler
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FMC_IRQHandler
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RCU_IRQHandler
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EXTI0_1_IRQHandler
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EXTI2_3_IRQHandler
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EXTI4_15_IRQHandler
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TSI_IRQHandler
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DMA_Channel0_IRQHandler
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DMA_Channel1_2_IRQHandler
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DMA_Channel3_4_IRQHandler
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ADC_CMP_IRQHandler
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TIMER0_BRK_UP_TRG_COM_IRQHandler
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TIMER0_Channel_IRQHandler
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TIMER1_IRQHandler
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TIMER2_IRQHandler
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TIMER5_DAC_IRQHandler
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TIMER13_IRQHandler
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TIMER14_IRQHandler
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TIMER15_IRQHandler
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TIMER16_IRQHandler
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I2C0_EV_IRQHandler
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I2C1_EV_IRQHandler
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SPI0_IRQHandler
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SPI1_IRQHandler
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USART0_IRQHandler
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USART1_IRQHandler
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CEC_IRQHandler
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I2C0_ER_IRQHandler
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I2C1_ER_IRQHandler
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I2C2_EV_IRQHandler
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I2C2_ER_IRQHandler
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USBD_LP_IRQHandler
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USBD_HP_IRQHandler
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USBDWakeUp_IRQHandler
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CAN0_TX_IRQHandler
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CAN0_RX0_IRQHandler
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CAN0_RX1_IRQHandler
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CAN0_SCE_IRQHandler
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SLCD_IRQHandler
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DMA_Channel5_6_IRQHandler
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SPI2_IRQHandler
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CAN1_TX_IRQHandler
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CAN1_RX0_IRQHandler
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CAN1_RX1_IRQHandler
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CAN1_SCE_IRQHandler
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B .
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ENDP
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ALIGN
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; user Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ENDP
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ALIGN
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ENDIF
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END
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