mirror of
https://github.com/EFeru/hoverboard-sideboard-hack-GD.git
synced 2025-07-27 17:49:32 +00:00
793 lines
17 KiB
C
793 lines
17 KiB
C
/*!
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\file gd32f1x0_dac.c
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\brief DAC driver
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*/
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/*
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Copyright (C) 2017 GigaDevice
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2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
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2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
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2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
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2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
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*/
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#include "gd32f1x0_dac.h"
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/*!
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\brief deinit DAC
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac_deinit(void)
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{
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rcu_periph_reset_enable(RCU_DACRST);
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rcu_periph_reset_disable(RCU_DACRST);
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}
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/*!
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\brief enable DAC0
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac0_enable(void)
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{
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DAC_CTL |= DAC_CTL_DEN0;
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}
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/*!
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\brief disable DAC0
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac0_disable(void)
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{
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DAC_CTL &= ~DAC_CTL_DEN0;
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}
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/*!
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\brief enable DAC0 DMA
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac0_dma_enable(void)
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{
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DAC_CTL |= DAC_CTL_DDMAEN0;
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}
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/*!
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\brief disable DAC0 DMA
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac0_dma_disable(void)
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{
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DAC_CTL &= ~DAC_CTL_DDMAEN0;
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}
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/*!
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\brief enable DAC0 output buffer
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac0_output_buffer_enable(void)
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{
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DAC_CTL &= ~DAC_CTL_DBOFF0;
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}
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/*!
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\brief disable DAC0 output buffer
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac0_output_buffer_disable(void)
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{
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DAC_CTL |= DAC_CTL_DBOFF0;
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}
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/*!
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\brief enable DAC0 trigger
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac0_trigger_enable(void)
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{
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DAC_CTL |= DAC_CTL_DTEN0;
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}
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/*!
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\brief disable DAC0 trigger
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac0_trigger_disable(void)
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{
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DAC_CTL &= ~DAC_CTL_DTEN0;
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}
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/*!
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\brief enable DAC0 software trigger
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac0_software_trigger_enable(void)
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{
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DAC_SWT |= DAC_SWT_SWTR0;
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}
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/*!
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\brief disable DAC0 software trigger
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac0_software_trigger_disable(void)
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{
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DAC_SWT &= ~DAC_SWT_SWTR0;
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}
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/*!
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\brief enable DAC0 interrupt(DAC0 DMA underrun interrupt)
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac0_interrupt_enable(void)
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{
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DAC_CTL |= DAC_CTL_DDUDRIE0;
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}
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/*!
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\brief disable DAC0 interrupt(DAC0 DMA underrun interrupt)
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac0_interrupt_disable(void)
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{
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DAC_CTL &= ~DAC_CTL_DDUDRIE0;
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}
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/*!
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\brief set DAC0 tgigger source
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\param[in] triggersource: external triggers of DAC
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\arg DAC_TRIGGER_T1_TRGO: trigger source is timer1 trgo
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\arg DAC_TRIGGER_T2_TRGO: trigger source is timer2 trgo
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\arg DAC_TRIGGER_T5_TRGO: trigger source is timer5 trgo
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\arg DAC_TRIGGER_T14_TRGO: trigger source is timer14 trgo
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\arg DAC_TRIGGER_EXTI_IT9: trigger source is exti interrupt line 9
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\arg DAC_TRIGGER_SOFTWARE: trigger source is software
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\param[out] none
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\retval none
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*/
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void dac0_trigger_source_config(uint32_t triggersource)
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{
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DAC_CTL &= ~DAC_CTL_DTSEL0;
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DAC_CTL |= triggersource;
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}
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/*!
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\brief get the last data output value of DAC0
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\param[in] none
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\param[out] none
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\retval DAC output data
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*/
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uint16_t dac0_output_value_get(void)
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{
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uint16_t data = 0U;
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data = (uint16_t)DAC0_DO;
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return data;
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}
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/*!
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\brief get the specified DAC0 flag(DAC0 DMA underrun flag)
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\param[in] none
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\param[out] none
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\retval the state of dac bit(SET or RESET)
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*/
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FlagStatus dac0_flag_get(void)
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{
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/* check the DMA underrun flag */
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if((uint8_t)RESET != (DAC_STAT & DAC_STAT_DDUDR0)){
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return SET;
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}else{
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return RESET;
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}
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}
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/*!
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\brief clear the specified DAC0 flag(DAC0 DMA underrun flag)
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac0_flag_clear(void)
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{
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DAC_STAT &= ~DAC_STAT_DDUDR0;
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}
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/*!
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\brief get the specified DAC0 interrupt flag(DAC0 DMA underrun interrupt flag)
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\param[in] none
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\param[out] none
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\retval the state of DAC interrupt flag(SET or RESET)
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*/
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FlagStatus dac0_interrupt_flag_get(void)
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{
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uint32_t ddudr_flag = 0U, ddudrie_flag = 0U;
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ddudr_flag = (DAC_STAT & DAC_STAT_DDUDR0);
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ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE0;
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/* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */
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if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){
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return SET;
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}else{
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return RESET;
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}
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}
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/*!
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\brief clear the specified DAC0 interrupt flag(DAC0 DMA underrun interrupt flag)
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\param[in] none
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\param[out] none
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\retval none
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*/
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void dac0_interrupt_flag_clear(void)
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{
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DAC_CTL &= ~DAC_CTL_DDUDRIE0;
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}
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/*!
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\brief set DAC0 data holding register value
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\param[in] dac_align
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\arg DAC_ALIGN_8B_R: data right 8b alignment
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\arg DAC_ALIGN_12B_R: data right 12b alignment
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\arg DAC_ALIGN_12B_L: data left 12b alignment
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\param[in] data: data to be loaded
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\param[out] none
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\retval none
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*/
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void dac0_data_set(uint32_t dac_align, uint16_t data)
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{
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switch(dac_align){
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/* data right 12b alignment */
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case DAC_ALIGN_12B_R:
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DAC0_R12DH = data;
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break;
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/* data left 12b alignment */
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case DAC_ALIGN_12B_L:
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DAC0_L12DH = data;
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break;
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/* data right 8b alignment */
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case DAC_ALIGN_8B_R:
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DAC0_R8DH = data;
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break;
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default:
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break;
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}
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}
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#ifdef GD32F170_190
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/*!
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\brief enable DAC
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\param[in] dac_periph
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\arg DACx(x =0,1)
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\param[out] none
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\retval none
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*/
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void dac_enable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL |= DAC_CTL_DEN0;
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}else{
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DAC_CTL |= DAC_CTL_DEN1;
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}
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}
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/*!
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\brief disable DAC
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\param[in] dac_periph
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\arg DACx(x =0,1)
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\param[out] none
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\retval none
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*/
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void dac_disable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL &= ~DAC_CTL_DEN0;
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}else{
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DAC_CTL &= ~DAC_CTL_DEN1;
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}
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}
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/*!
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\brief enable DAC DMA function
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\param[in] dac_periph
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\arg DACx(x=0,1)
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\param[out] none
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\retval none
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*/
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void dac_dma_enable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL |= DAC_CTL_DDMAEN0;
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}else{
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DAC_CTL |= DAC_CTL_DDMAEN1;
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}
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}
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/*!
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\brief disable DAC DMA function
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\param[in] dac_periph
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\arg DACx(x=0,1)
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\param[out] none
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\retval none
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*/
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void dac_dma_disable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL &= ~DAC_CTL_DDMAEN0;
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}else{
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DAC_CTL &= ~DAC_CTL_DDMAEN1;
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}
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}
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/*!
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\brief enable DAC output buffer
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\param[in] dac_periph
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\arg DACx(x =0,1)
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\param[out] none
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\retval none
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*/
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void dac_output_buffer_enable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL &= ~DAC_CTL_DBOFF0;
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}else{
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DAC_CTL &= ~DAC_CTL_DBOFF1;
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}
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}
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/*!
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\brief disable DAC output buffer
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\param[in] dac_periph
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\arg DACx(x =0,1)
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\param[out] none
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\retval none
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*/
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void dac_output_buffer_disable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL |= DAC_CTL_DBOFF0;
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}else{
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DAC_CTL |= DAC_CTL_DBOFF1;
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}
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}
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/*!
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\brief enable DAC trigger
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\param[in] dac_periph
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\arg DACx(x =0,1)
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\param[out] none
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\retval none
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*/
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void dac_trigger_enable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL |= DAC_CTL_DTEN0;
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}else{
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DAC_CTL |= DAC_CTL_DTEN1;
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}
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}
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/*!
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\brief disable DAC trigger
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\param[in] dac_periph
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\arg DACx(x =0,1)
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\param[out] none
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\retval none
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*/
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void dac_trigger_disable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL &= ~DAC_CTL_DTEN0;
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}else{
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DAC_CTL &= ~DAC_CTL_DTEN1;
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}
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}
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/*!
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\brief enable DAC software trigger
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\param[in] dac_periph
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\arg DACx(x =0,1)
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\retval none
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*/
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void dac_software_trigger_enable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_SWT |= DAC_SWT_SWTR0;
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}else{
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DAC_SWT |= DAC_SWT_SWTR1;
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}
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}
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/*!
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\brief disable DAC software trigger
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\param[in] dac_periph
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\arg DACx(x =0,1)
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\param[out] none
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\retval none
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*/
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void dac_software_trigger_disable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_SWT &= ~DAC_SWT_SWTR0;
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}else{
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DAC_SWT &= ~DAC_SWT_SWTR1;
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}
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}
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/*!
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\brief get DAC output value
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\param[in] dac_periph
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\arg DACx(x=0,1)
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\param[out] none
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\retval DAC output data
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*/
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uint16_t dac_output_value_get(uint32_t dac_periph)
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{
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uint16_t data = 0U;
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if(DAC0 == dac_periph){
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data = (uint16_t)DAC0_DO;
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}else{
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data = (uint16_t)DAC1_DO;
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}
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return data;
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}
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/*!
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\brief enable DAC interrupt(DAC0 DMA underrun interrupt)
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\param[in] dac_periph
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\arg DACx(x=0,1)
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\param[out] none
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\retval none
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*/
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void dac_interrupt_enable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL |= DAC_CTL_DDUDRIE0;
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}else{
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DAC_CTL |= DAC_CTL_DDUDRIE1;
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}
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}
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/*!
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\brief disable DAC interrupt(DAC0 DMA underrun interrupt)
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\param[in] dac_periph
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\arg DACx(x=0,1)
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\param[out] none
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\retval none
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*/
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void dac_interrupt_disable(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_CTL &= ~DAC_CTL_DDUDRIE0;
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}else{
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DAC_CTL &= ~DAC_CTL_DDUDRIE1;
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}
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}
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/*!
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\brief set DAC trigger source
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\param[in] dac_periph
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\arg DACx(x =0,1)
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\param[in] triggersource: external triggers of DAC
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\arg DAC_TRIGGER_T1_TRGO: trigger source is timer1 trgo
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\arg DAC_TRIGGER_T2_TRGO: trigger source is timer2 trgo
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\arg DAC_TRIGGER_T5_TRGO: trigger source is timer5 trgo
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\arg DAC_TRIGGER_T14_TRGO: trigger source is timer14 trgo
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\arg DAC_TRIGGER_EXTI_IT9: trigger source is exti interrupt line 9
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\arg DAC_TRIGGER_SOFTWARE: trigger source is software
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\param[out] none
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\retval none
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*/
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void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource)
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{
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if(DAC0 == dac_periph){
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DAC_CTL &= ~DAC_CTL_DTSEL0;
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DAC_CTL |= triggersource;
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}else{
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DAC_CTL &= ~DAC_CTL_DTSEL1;
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DAC_CTL |= (triggersource <<16);
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}
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}
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/*!
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\brief get the specified DAC flag(DAC DMA underrun flag)
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\param[in] dac_periph
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\arg DACx(x=0,1)
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\param[out] none
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\retval the state of dac bit(SET or RESET)
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*/
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FlagStatus dac_flag_get(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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/* check the DMA underrun flag */
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if(RESET != (DAC_STAT & DAC_STAT_DDUDR0)){
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return SET;
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}else{
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return RESET;
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}
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}else{
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/* check the DMA underrun flag */
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if(RESET != (DAC_STAT & DAC_STAT_DDUDR1)){
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return SET;
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}else{
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return RESET;
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}
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}
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}
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/*!
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\brief clear the specified DAC flag(DAC DMA underrun flag)
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\param[in] dac_periph
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\arg DACx(x=0,1)
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\param[out] none
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\retval none
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*/
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void dac_flag_clear(uint32_t dac_periph)
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{
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if(DAC0 == dac_periph){
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DAC_STAT |= DAC_STAT_DDUDR0;
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}else{
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DAC_STAT |= DAC_STAT_DDUDR1;
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}
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}
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/*!
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\brief get the specified DAC interrupt flag(DAC DMA underrun interrupt flag)
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\param[in] dac_periph
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\arg DACx(x=0,1)
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\param[out] none
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\retval the state of DAC interrupt flag(SET or RESET)
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*/
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FlagStatus dac_interrupt_flag_get(uint32_t dac_periph)
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{
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uint32_t ddudr_flag = 0U, ddudrie_flag = 0U;
|
|
if(DAC0 == dac_periph){
|
|
ddudr_flag = DAC_STAT & DAC_STAT_DDUDR0;
|
|
ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE0;
|
|
/* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */
|
|
if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){
|
|
return SET;
|
|
}else{
|
|
return RESET;
|
|
}
|
|
}else{
|
|
ddudr_flag = DAC_STAT & DAC_STAT_DDUDR1;
|
|
ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE1;
|
|
/* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */
|
|
if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){
|
|
return SET;
|
|
}else{
|
|
return RESET;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag)
|
|
\param[in] dac_periph
|
|
\arg DACx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dac_interrupt_flag_clear(uint32_t dac_periph)
|
|
{
|
|
if(DAC0 == dac_periph){
|
|
DAC_STAT |= DAC_STAT_DDUDR0;
|
|
}else{
|
|
DAC_STAT |= DAC_STAT_DDUDR1;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief enable DAC concurrent mode
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dac_concurrent_enable(void)
|
|
{
|
|
uint32_t ctl = 0U;
|
|
ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
|
|
DAC_CTL |= (ctl);
|
|
}
|
|
|
|
/*!
|
|
\brief disable DAC concurrent mode
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dac_concurrent_disable(void)
|
|
{
|
|
uint32_t ctl = 0U;
|
|
ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
|
|
DAC_CTL &= (~ctl);
|
|
}
|
|
|
|
/*!
|
|
\brief enable DAC concurrent software trigger function
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dac_concurrent_software_trigger_enable(void)
|
|
{
|
|
uint32_t swt = 0U;
|
|
swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
|
|
DAC_SWT |= (swt);
|
|
}
|
|
|
|
/*!
|
|
\brief disable DAC concurrent software trigger function
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dac_concurrent_software_trigger_disable(void)
|
|
{
|
|
uint32_t swt = 0U;
|
|
swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
|
|
DAC_SWT &= (~swt);
|
|
}
|
|
|
|
/*!
|
|
\brief enable DAC concurrent buffer funcution
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dac_concurrent_output_buffer_enable(void)
|
|
{
|
|
uint32_t ctl = 0U;
|
|
ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
|
|
DAC_CTL &= (~ctl);
|
|
}
|
|
|
|
/*!
|
|
\brief disable DAC concurrent buffer funcution
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dac_concurrent_output_buffer_disable(void)
|
|
{
|
|
uint32_t ctl = 0U;
|
|
ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
|
|
DAC_CTL |= (ctl);
|
|
}
|
|
|
|
/*!
|
|
\brief enable DAC concurrent interrupt funcution
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dac_concurrent_interrupt_enable(void)
|
|
{
|
|
DAC_CTL |= DAC_CTL_DDUDRIE0;
|
|
DAC_CTL |= DAC_CTL_DDUDRIE1;
|
|
}
|
|
|
|
/*!
|
|
\brief disable DAC concurrent interrupt funcution
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dac_concurrent_interrupt_disable(void)
|
|
{
|
|
DAC_CTL &= ~DAC_CTL_DDUDRIE0;
|
|
DAC_CTL &= ~DAC_CTL_DDUDRIE1;
|
|
}
|
|
|
|
/*!
|
|
\brief set the DAC specified data holding register value
|
|
\param[in] dac_periph
|
|
\arg DACx(x=0,1)
|
|
\param[in] dac_align
|
|
\arg DAC_ALIGN_8B_R: data right 8b alignment
|
|
\arg DAC_ALIGN_12B_R: data right 12b alignment
|
|
\arg DAC_ALIGN_12B_L: data left 12b alignment
|
|
\param[in] data: data to be loaded
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data)
|
|
{
|
|
if(DAC0 == dac_periph){
|
|
switch(dac_align){
|
|
/* data right 12b alignment */
|
|
case DAC_ALIGN_12B_R:
|
|
DAC0_R12DH = data;
|
|
break;
|
|
/* data left 12b alignment */
|
|
case DAC_ALIGN_12B_L:
|
|
DAC0_L12DH = data;
|
|
break;
|
|
/* data right 8b alignment */
|
|
case DAC_ALIGN_8B_R:
|
|
DAC0_R8DH = data;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}else{
|
|
switch(dac_align){
|
|
/* data right 12b alignment */
|
|
case DAC_ALIGN_12B_R:
|
|
DAC1_R12DH = data;
|
|
break;
|
|
/* data left 12b alignment */
|
|
case DAC_ALIGN_12B_L:
|
|
DAC1_L12DH = data;
|
|
break;
|
|
/* data right 8b alignment */
|
|
case DAC_ALIGN_8B_R:
|
|
DAC1_R8DH = data;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief set DAC concurrent mode data holding register value
|
|
\param[in] dac_align
|
|
\arg DAC_ALIGN_8B_R: data right 8b alignment
|
|
\arg DAC_ALIGN_12B_R: data right 12b alignment
|
|
\arg DAC_ALIGN_12B_L: data left 12b alignment
|
|
\param[in] data1: data to be loaded
|
|
\param[in] data2: data to be loaded
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data1, uint16_t data2)
|
|
{
|
|
uint32_t data = 0U;
|
|
switch(dac_align){
|
|
/* data right 12b alignment */
|
|
case DAC_ALIGN_12B_R:
|
|
data = ((uint32_t)data2 << 16U) | data1;
|
|
DACC_R12DH = data;
|
|
break;
|
|
/* data left 12b alignment */
|
|
case DAC_ALIGN_12B_L:
|
|
data = ((uint32_t)data2 << 16U) | data1;
|
|
DACC_L12DH = data;
|
|
break;
|
|
/* data right 8b alignment */
|
|
case DAC_ALIGN_8B_R:
|
|
data = ((uint32_t)data2 << 8U) | data1;
|
|
DACC_R8DH = data;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
#endif /* GD32F170_190 */
|