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240 lines
12 KiB
C
240 lines
12 KiB
C
/*!
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\file gd32f1x0_fmc.h
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\brief definitions for the FMC
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*/
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/*
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Copyright (C) 2017 GigaDevice
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2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
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2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
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2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
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2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
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*/
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#ifndef GD32F1X0_FMC_H
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#define GD32F1X0_FMC_H
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#include "gd32f1x0.h"
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/* FMC and option byte definition */
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#define FMC FMC_BASE /*!< FMC register base address */
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#define OB OB_BASE /*!< option byte base address */
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/* registers definitions */
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#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
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#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */
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#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */
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#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */
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#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */
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#define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */
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#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */
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#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC write protection register */
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#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */
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#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
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#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */
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#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/
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#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */
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#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */
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/* bits definitions */
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/* FMC_WS */
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#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
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/* FMC_KEY */
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#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash unlock key bits */
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/* FMC_OBKEY */
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#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */
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/* FMC_STAT */
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#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */
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#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */
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#define FMC_STAT_WPERR BIT(4) /*!< flash write protection error flag bit */
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#define FMC_STAT_ENDF BIT(5) /*!< flash end of operation flag bit */
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/* FMC_CTL */
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#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */
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#define FMC_CTL_PER BIT(1) /*!< main flash page erase bit */
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#define FMC_CTL_MER BIT(2) /*!< main flash mass erase bit */
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#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */
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#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */
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#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */
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#define FMC_CTL_LK BIT(7) /*!< flash lock bit */
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#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
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#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */
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#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
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#define FMC_CTL_OBRLD BIT(13) /*!< option bytes reload bit */
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/* FMC_ADDR */
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#define FMC_ADDR_ADDR BITS(0,31) /*!< flash command address bits */
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/* FMC_OBSTAT */
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#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit */
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#define FMC_OBSTAT_PLVL_BIT0 BIT(1) /*!< protection level bit 0 */
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#define FMC_OBSTAT_PLVL_BIT1 BIT(2) /*!< protection level bit 1 */
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#define FMC_OBSTAT_USER BITS(8,15) /*!< option bytes user bits */
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#define FMC_OBSTAT_DATA BITS(16,31) /*!< option byte data bits */
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/* FMC_WSEN */
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#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */
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#ifdef GD32F170_190
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#define FMC_WSEN_BPEN BIT(1) /*!< FMC bit program enable bit */
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#endif /* GD32F170_190 */
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/* FMC_PID */
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#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
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/* constants definitions */
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/* fmc state */
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typedef enum
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{
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FMC_READY, /*!< the operation has been completed */
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FMC_BUSY, /*!< the operation is in progress */
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FMC_PGERR, /*!< program error */
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FMC_WPERR, /*!< erase/program protection error */
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FMC_TOERR, /*!< timeout error */
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FMC_OB_HSPC /*!< option byte security protection code high */
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}fmc_state_enum;
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/* unlock key */
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#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
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#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
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/* wait state counter value */
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#define WS_WSCNT_0 ((uint8_t)0x00U) /*!< 0 wait state added */
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#define WS_WSCNT_1 ((uint8_t)0x01U) /*!< 1 wait state added */
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#define WS_WSCNT_2 ((uint8_t)0x02U) /*!< 2 wait state added */
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/* read protect configure */
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#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */
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#define FMC_LSPC ((uint8_t)0xBBU) /*!< low security protection, any value except 0xA5 or 0xCC */
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#define FMC_HSPC ((uint8_t)0xCCU) /*!< high security protection */
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/* option byte write protection */
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#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */
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#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */
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/* option byte software/hardware free watchdog timer */
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#define OBUSER_NWDG_HW(regval) (BIT(0) & ((uint32_t)(regval) << 0))
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#define OB_FWDGT_HW OBUSER_NWDG_HW(0) /*!< hardware free watchdog timer */
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#define OB_FWDGT_SW OBUSER_NWDG_HW(1) /*!< software free watchdog timer */
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/* option byte reset or not entering deep sleep mode */
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#define OBUSER_NRST_DPSLP(regval) (BIT(1) & ((uint32_t)(regval) << 1))
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#define OB_DEEPSLEEP_RST OBUSER_NRST_DPSLP(0) /*!< generate a reset instead of entering deepsleep mode */
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#define OB_DEEPSLEEP_NRST OBUSER_NRST_DPSLP(1) /*!< no reset when entering deepsleep mode */
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/* option byte reset or not entering standby mode */
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#define OBUSER_NRST_STDBY(regval) (BIT(2) & ((uint32_t)(regval) << 2))
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#define OB_STDBY_RST OBUSER_NRST_STDBY(0) /*!< generate a reset instead of entering standby mode */
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#define OB_STDBY_NRST OBUSER_NRST_STDBY(1) /*!< no reset when entering deepsleep mode */
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/* option byte OB_BOOT1_n set */
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#define OBUSER_BOOT1_N(regval) (BIT(4) & ((uint32_t)(regval) << 4))
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#define OB_BOOT1_SET_1 OBUSER_BOOT1_N(0) /*!< BOOT1 bit is 1 */
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#define OB_BOOT1_SET_0 OBUSER_BOOT1_N(1) /*!< BOOT1 bit is 0 */
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/* option byte VDDA monitor enable/disable */
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#define OBUSER_VDDA_VISOR(regval) (BIT(5) & ((uint32_t)(regval) << 5))
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#define OB_VDDA_DISABLE OBUSER_VDDA_VISOR(0) /*!< disable VDDA monitor */
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#define OB_VDDA_ENABLE OBUSER_VDDA_VISOR(1) /*!< enable VDDA monitor */
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/* option byte SRAM parity enable/disable */
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#define OBUSER_SRAM_PARITY(regval) (BIT(6) & ((uint32_t)(regval) << 6))
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#define OB_SRAM_PARITY_ENABLE OBUSER_SRAM_PARITY(0) /*!< enable SRAM parity check */
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#define OB_SRAM_PARITY_DISABLE OBUSER_SRAM_PARITY(1) /*!< disable SRAM parity check */
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/* option byte security protection level in FMC_OBSTAT register */
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#define OB_OBSTAT_PLEVEL_NO ((uint32_t)0x00000000U) /*!< no security protection */
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#define OB_OBSTAT_PLEVEL_LOW ((uint32_t)0x00000002U) /*!< low security protection */
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#define OB_OBSTAT_PLEVEL_HIGH ((uint32_t)0x00000006U) /*!< high security protection */
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/* option byte user mask */
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#define OB_USER_MASK ((uint8_t)0x88U) /*!< OB_USER reserved bit mask */
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/* option byte data address */
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#define OB_DATA_ADDR0 ((uint32_t)0x1FFFF804U) /*!< option byte data address 0 */
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#define OB_DATA_ADDR1 ((uint32_t)0x1FFFF806U) /*!< option byte data address 1 */
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/* FMC flags */
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#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */
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#define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */
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#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */
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#define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */
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/* FMC interrupt enable */
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#define FMC_INTEN_END FMC_CTL_ENDIE /*!< enable FMC end of operation interrupt */
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#define FMC_INTEN_ERR FMC_CTL_ERRIE /*!< enable FMC error interrupt */
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/* FMC time out */
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#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< count to judge of FMC timeout */
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/* function declarations */
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/* FMC main memory programming functions */
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/* unlock the main FMC operation */
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void fmc_unlock(void);
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/* lock the main FMC operation */
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void fmc_lock(void);
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/* set the wait state counter value */
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void fmc_wscnt_set(uint8_t wscnt);
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/* fmc wait state enable */
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void fmc_wait_state_enable(void);
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/* fmc wait state disable */
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void fmc_wait_state_disable(void);
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/* FMC erase page */
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fmc_state_enum fmc_page_erase(uint32_t page_address);
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/* FMC erase whole chip */
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fmc_state_enum fmc_mass_erase(void);
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/* FMC program a word at the corresponding address */
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fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
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/* FMC program a half word at the corresponding address */
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fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
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#ifdef GD32F170_190
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/* FMC program a word at the corresponding address without erasing */
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fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data);
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#endif /* GD32F170_190 */
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/* FMC option bytes programming functions */
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/* unlock the option byte operation */
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void ob_unlock(void);
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/* lock the option byte operation */
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void ob_lock(void);
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/* reload the option byte and generate a system reset */
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void ob_reset(void);
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/* erase option byte */
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fmc_state_enum ob_erase(void);
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/* enable option byte write protection (OB_WP) */
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fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
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/* configure read out protect */
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fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
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/* write the FMC option byte user */
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fmc_state_enum ob_user_write(uint8_t ob_user);
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/* write the FMC option byte data */
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fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
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/* get the FMC option byte OB_USER */
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uint8_t ob_user_get(void);
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/* get the FMC option byte OB_DATA */
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uint16_t ob_data_get(void);
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/* get the FMC option byte write protection */
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uint16_t ob_write_protection_get(void);
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/* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */
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uint32_t ob_obstat_plevel_get(void);
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/* FMC interrupts and flags management functions */
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/* enable FMC interrupt */
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void fmc_interrupt_enable(uint32_t interrupt);
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/* disable FMC interrupt */
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void fmc_interrupt_disable(uint32_t interrupt);
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/* get flag set or reset */
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FlagStatus fmc_flag_get(uint32_t flag);
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/* clear the FMC pending flag */
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void fmc_flag_clear(uint32_t flag);
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/* return the FMC state */
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fmc_state_enum fmc_state_get(void);
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/* check FMC ready or not */
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fmc_state_enum fmc_ready_wait(uint32_t timeout);
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#endif /* GD32F1X0_FMC_H */
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