mirror of
https://github.com/EFeru/hoverboard-sideboard-hack-GD.git
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446 lines
13 KiB
C
446 lines
13 KiB
C
/*!
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\file gd32f1x0_slcd.c
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\brief SLCD driver
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*/
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/*
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Copyright (C) 2017 GigaDevice
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2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
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2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
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2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
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2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
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*/
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#ifdef GD32F170_190
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#include "gd32f1x0_slcd.h"
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#include "gd32f1x0_rcu.h"
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/*!
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\brief SLCD reset
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\param[in] none
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\param[out] none
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\retval none
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*/
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void slcd_deinit(void)
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{
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rcu_periph_reset_enable(RCU_SLCDRST);
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rcu_periph_reset_disable(RCU_SLCDRST);
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}
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/*!
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\brief get the SLCD status flag
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\param[in] slcd_flag: the adc status flag bits
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\arg SLCD_FLAG_ON: SLCD controller on flag
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\arg SLCD_FLAG_SOF: start of frame flag
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\arg SLCD_FLAG_UPR: SLCD data update request flag
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\arg SLCD_FLAG_UPD: update LCDS data done flag
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\arg SLCD_FLAG_VRDY: SLCD voltage ready flag
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\arg SLCD_FLAG_SYN: SLCD CFG register synchronization flag
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\param[out] none
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\retval FlagStatus: SET or RESET
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*/
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FlagStatus slcd_flag_get(uint8_t slcd_flag)
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{
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if(SLCD_STAT & slcd_flag){
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return SET;
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}else{
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return RESET;
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}
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}
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/*!
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\brief get the SLCD interrupt flag
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\param[in] slcd_interrupt: the adc interrupt flag bits
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\arg SLCD_INT_FLAG_SOF: start of frame interrupt
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\arg SLCD_INT_FLAG_UPD: SLCD update done interrupt
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\param[out] none
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\retval FlagStatus: SET or RESET
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*/
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FlagStatus slcd_interrupt_flag_get(uint8_t slcd_interrupt)
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{
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FlagStatus interrupt_flag = RESET;
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uint32_t state;
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/* check the interrupt bits */
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switch(slcd_interrupt){
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case SLCD_INT_FLAG_SOF:
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state = SLCD_STAT & SLCD_FLAG_SOF;
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if((SLCD_CFG & SLCD_CFG_SOFIE) && state){
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interrupt_flag = SET;
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}
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break;
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case SLCD_INT_FLAG_UPD:
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state = SLCD_STAT & SLCD_FLAG_UPD;
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if((SLCD_CFG & SLCD_CFG_UPDIE) && state){
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interrupt_flag = SET;
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}
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break;
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default:
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break;
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}
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return interrupt_flag;
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}
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/*!
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\brief clear the SLCD flag
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\param[in] slcd_flag: the adc status flag bits
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\arg SLCD_FLAG_SOF: start of frame flag
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\arg SLCD_FLAG_UPD: update LCDS data done flag
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\param[out] none
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\retval none
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*/
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void slcd_flag_clear(uint8_t slcd_flag)
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{
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/* check the interrupt bits */
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switch(slcd_flag){
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case SLCD_FLAG_SOF:
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SLCD_STATC |= SLCD_STATC_SOFC;
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break;
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case SLCD_FLAG_UPD:
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SLCD_STATC |= SLCD_STATC_UPDC;
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break;
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default:
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break;
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}
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}
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/*!
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\brief clear the SLCD interrupt flag
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\param[in] slcd_interrupt: the adc interrupt bits
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\arg SLCD_INT_FLAG_SOF: start of frame interrupt
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\arg SLCD_INT_FLAG_UPD: SLCD update done interrupt
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\param[out] none
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\retval none
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*/
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void slcd_interrupt_flag_clear(uint8_t slcd_interrupt)
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{
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/* check the interrupt bits */
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switch(slcd_interrupt){
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case SLCD_INT_FLAG_SOF:
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SLCD_STATC |= SLCD_STATC_SOFC;
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break;
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case SLCD_INT_FLAG_UPD:
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SLCD_STATC |= SLCD_STATC_UPDC;
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break;
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default:
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break;
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}
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}
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/*!
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\brief the SLCD interrupt config
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\param[in] slcd_interrupt: the adc interrupt bits
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\arg SLCD_INT_SOF: start of frame interrupt
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\arg SLCD_INT_UPD: SLCD update done interrupt
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\param[out] none
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\retval none
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*/
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void slcd_interrupt_config(uint8_t slcd_interrupt,ControlStatus newvalue)
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{
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/* ENABLE or DISABLE the interrupt */
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if(newvalue){
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/* select the interrupt source */
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switch(slcd_interrupt){
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case SLCD_INT_SOF:
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SLCD_CFG |= (uint32_t) SLCD_CFG_SOFIE;
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break;
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case SLCD_INT_UPD:
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SLCD_CFG |= (uint32_t) SLCD_CFG_UPDIE;
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break;
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default:
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break;
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}
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}else{
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switch(slcd_interrupt){
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/* select the interrupt source */
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case SLCD_INT_SOF:
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SLCD_CFG &= (uint32_t)~(SLCD_CFG_SOFIE);
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break;
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case SLCD_INT_UPD:
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SLCD_CFG &= (uint32_t)~(SLCD_CFG_UPDIE);
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break;
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default:
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break;
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}
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}
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}
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/*!
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\brief SLCD bias voltage select
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\param[in] bias_voltage: the SLCD voltage bias
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\arg SLCD_BIAS_1_4: 1/4 voltage bias
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\arg SLCD_BIAS_1_2: 1/2 voltage bias
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\arg SLCD_BIAS_1_3: 1/3 voltage bias
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\param[out] none
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\retval none
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*/
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void slcd_bias_voltage_select(uint32_t bias_voltage)
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{
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SLCD_CTL &= (uint32_t)~(SLCD_CTL_BIAS);
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SLCD_CTL |= (uint32_t)bias_voltage;
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}
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/*!
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\brief SLCD duty cycle select
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\param[in] duty: the adc flag bits
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\arg SLCD_DUTY_STATIC: static dutycycle
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\arg SLCD_DUTY_1_2: 1/2 dutycycle
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\arg SLCD_DUTY_1_3: 1/3 dutycycle
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\arg SLCD_DUTY_1_4: 1/4 dutycycle
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\arg SLCD_DUTY_1_6: 1/6 dutycycle
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\arg SLCD_DUTY_1_8: 1/8 dutycycle
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\param[out] none
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\retval none
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*/
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void slcd_duty_select(uint32_t duty)
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{
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SLCD_CTL &= (uint32_t)~(SLCD_CTL_DUTY);
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SLCD_CTL |= (uint32_t)duty;
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}
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/*!
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\brief config the prescaler and the divider of SLCD clock
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fSLCD = finclk/( pow( 2 , PRE )* DIV )
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\param[in] prescaler: the prescaler factor
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\arg SLCD_PRESCALER_1: PRE = 0
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\arg SLCD_PRESCALER_2: PRE = 1
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\arg SLCD_PRESCALER_4: PRE = 2
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\arg SLCD_PRESCALER_8: PRE = 3
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\arg SLCD_PRESCALER_16: PRE = 4
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\arg SLCD_PRESCALER_32: PRE = 5
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\arg SLCD_PRESCALER_64: PRE = 6
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\arg SLCD_PRESCALER_128: PRE = 7
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\arg SLCD_PRESCALER_256: PRE = 8
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\arg SLCD_PRESCALER_512: PRE = 9
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\arg SLCD_PRESCALER_1024: PRE = 10
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\arg SLCD_PRESCALER_2048: PRE = 11
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\arg SLCD_PRESCALER_4096: PRE = 12
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\arg SLCD_PRESCALER_8192: PRE = 13
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\arg SLCD_PRESCALER_16384: PRE = 14
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\arg SLCD_PRESCALER_32768: PRE = 15
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\param[in] divider: the divider factor
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\arg SLCD_DIVIDER_x: x= 16..31 ,DIV = 16..31
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\param[out] none
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\retval none
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*/
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void slcd_clock_config(uint32_t prescaler,uint32_t divider)
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{
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uint32_t cfg;
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/* config the prescaler and the divider */
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cfg = SLCD_CFG;
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cfg &= (uint32_t)~(SLCD_CFG_PSC | SLCD_CFG_DIV);
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cfg |= (uint32_t)(prescaler | divider);
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SLCD_CFG = cfg;
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}
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/*!
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\brief SLCD blink mode config
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\param[in] mode: the prescaler factor
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\arg SLCD_BLINKMODE_OFF: blink disabled
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\arg SLCD_BLINKMODE_SEG0_COM0: blink enabled on SEG[0], COM[0]
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\arg SLCD_BLINKMODE_SEG0_ALLCOM: blink enabled on SEG[0], all COM
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\arg SLCD_BLINKMODE_ALLSEG_ALLCOM: blink enabled on all SEG and all COM
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\param[in] blink_divider: the divider factor
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\arg SLCD_BLINK_FREQUENCY_DIV8: blink frequency = fSLCD/8
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\arg SLCD_BLINK_FREQUENCY_DIV16: blink frequency = fSLCD/16
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\arg SLCD_BLINK_FREQUENCY_DIV32: blink frequency = fSLCD/32
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\arg SLCD_BLINK_FREQUENCY_DIV64: blink frequency = fSLCD/64
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\arg SLCD_BLINK_FREQUENCY_DIV128: blink frequency = fSLCD/128
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\arg SLCD_BLINK_FREQUENCY_DIV256: blink frequency = fSLCD/256
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\arg SLCD_BLINK_FREQUENCY_DIV512: blink frequency = fSLCD/512
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\arg SLCD_BLINK_FREQUENCY_DIV1024: blink frequency = fSLCD/1024
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\param[out] none
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\retval none
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*/
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void slcd_blink_mode_config(uint32_t mode,uint32_t blink_divider)
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{
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SLCD_CFG &= (uint32_t)~(SLCD_CFG_BLKMOD | SLCD_CFG_BLKDIV);
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SLCD_CFG |= (uint32_t)(mode | blink_divider);
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}
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/*!
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\brief SLCD contrast ratio config
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\param[in] contrast_ratio: specify the VSLCD voltage ,when chosing the internal voltage source
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\arg SLCD_CONTRAST_LEVEL_0: maximum SLCD Voltage = 2.60V
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\arg SLCD_CONTRAST_LEVEL_1: maximum SLCD Voltage = 2.73V
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\arg SLCD_CONTRAST_LEVEL_2: maximum SLCD Voltage = 2.86V
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\arg SLCD_CONTRAST_LEVEL_3: maximum SLCD Voltage = 2.99V
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\arg SLCD_CONTRAST_LEVEL_4: maximum SLCD Voltage = 3.12V
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\arg SLCD_CONTRAST_LEVEL_5: maximum SLCD Voltage = 3.25V
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\arg SLCD_CONTRAST_LEVEL_6: maximum SLCD Voltage = 3.38V
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\arg SLCD_CONTRAST_LEVEL_7: maximum SLCD Voltage = 3.51V
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\param[out] none
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\retval none
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*/
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void slcd_contrast_ratio_config(uint32_t contrast_ratio)
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{
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uint32_t cfg;
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/* config the contrast ratio */
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cfg = SLCD_CFG;
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cfg &= (uint32_t)~(SLCD_CFG_CONR);
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cfg |= (uint32_t)contrast_ratio;
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SLCD_CFG = cfg;
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}
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/*!
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\brief SLCD dead time duration config
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\param[in] dead_time: configure the length of the dead time between frames
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\arg SLCD_DEADTIME_PERIOD_0: no dead time
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\arg SLCD_DEADTIME_PERIOD_1: 1 phase inserted between couple of frame
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\arg SLCD_DEADTIME_PERIOD_2: 2 phase inserted between couple of frame
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\arg SLCD_DEADTIME_PERIOD_3: 3 phase inserted between couple of frame
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\arg SLCD_DEADTIME_PERIOD_4: 4 phase inserted between couple of frame
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\arg SLCD_DEADTIME_PERIOD_5: 5 phase inserted between couple of frame
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\arg SLCD_DEADTIME_PERIOD_6: 6 phase inserted between couple of frame
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\arg SLCD_DEADTIME_PERIOD_7: 7 phase inserted between couple of frame
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\param[out] none
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\retval none
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*/
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void slcd_dead_time_config(uint32_t dead_time)
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{
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uint32_t cfg;
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/* config dead time duration */
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cfg = SLCD_CFG;
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cfg &= (uint32_t)~(SLCD_CFG_DTD);
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cfg |= (uint32_t)dead_time;
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SLCD_CFG = cfg;
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}
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/*!
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\brief SLCD pulse on duration config
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\param[in] duration: configure the length of the dead time between frames
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\arg SLCD_PULSEON_DURATION_0: pulse on duration = 0
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\arg SLCD_PULSEON_DURATION_1: pulse on duration = 1*1/fPRE
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\arg SLCD_PULSEON_DURATION_2: pulse on duration = 2*1/fPRE
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\arg SLCD_PULSEON_DURATION_3: pulse on duration = 3*1/fPRE
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\arg SLCD_PULSEON_DURATION_4: pulse on duration = 4*1/fPRE
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\arg SLCD_PULSEON_DURATION_5: pulse on duration = 5*1/fPRE
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\arg SLCD_PULSEON_DURATION_6: pulse on duration = 6*1/fPRE
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\arg SLCD_PULSEON_DURATION_7: pulse on duration = 7*1/fPRE
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\param[out] none
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\retval none
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*/
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void slcd_pulse_on_duration_config(uint32_t duration)
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{
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uint32_t cfg;
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/* config pulse on duration */
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cfg = SLCD_CFG;
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cfg &= (uint32_t)~(SLCD_CFG_PULSE);
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cfg |= (uint32_t)duration;
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SLCD_CFG = cfg;
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}
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/*!
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\brief SLCD common/segment pad select
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\param[in] NewValue: ENABLE or DISABLE
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\arg ENABLE: LCD_COM[7:4] pad select LCD_SEG[31:28]
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\arg DISABLE: LCD_COM[7:4] pad select LCD_COM[7:4]
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\param[out] none
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\retval none
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*/
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void slcd_com_seg_remap(ControlStatus newvalue)
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{
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if( ENABLE == newvalue ){
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SLCD_CTL |= SLCD_CTL_COMS;
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}else{
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SLCD_CTL &= ~(SLCD_CTL_COMS);
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}
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}
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/*!
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\brief SLCD voltage source select
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\param[in] voltage_source: the SLCD voltage source
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\arg SLCD_VOLTAGE_INTERNAL: internal source
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\arg SLCD_VOLTAGE_EXTERNAL: external source (VSLCD pin)
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\param[out] none
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\retval none
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*/
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void slcd_voltage_source_select(uint8_t voltage_source)
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{
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if( SLCD_VOLTAGE_EXTERNAL == voltage_source ){
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SLCD_CTL |= SLCD_CTL_VSRC;
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}else{
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SLCD_CTL &= ~(SLCD_CTL_VSRC);
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}
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}
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/*!
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\brief enable or disable permanent high drive
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\param[in] NewValue: ENABLE or DISABLE
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\param[out] none
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\retval none
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*/
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void slcd_high_drive_config(ControlStatus newvalue)
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{
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if( ENABLE == newvalue ){
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SLCD_CFG |= SLCD_CFG_HDEN;
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}else{
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SLCD_CFG &= ~(SLCD_CFG_HDEN);
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}
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}
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/*!
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\brief SLCD voltage source select
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\param[in] data_reg: the SLCD data register
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\arg SLCD_DATA_REG0: SLCD_DATA register 0
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\arg SLCD_DATA_REG1: SLCD_DATA Register 1
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\arg SLCD_DATA_REG2: SLCD_DATA register 2
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\arg SLCD_DATA_REG3: SLCD_DATA Register 3
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\arg SLCD_DATA_REG4: SLCD_DATA register 4
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\arg SLCD_DATA_REG5: SLCD_DATA Register 5
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\arg SLCD_DATA_REG6: SLCD_DATA register 6
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\arg SLCD_DATA_REG7: SLCD_DATA Register 7
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\param[in] data: the data write to the register
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\param[out] none
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\retval none
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*/
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void slcd_data_register_write(uint32_t data_reg,uint32_t data)
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{
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volatile uint32_t *pdata;
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/* point to DATA register */
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pdata = &SLCD_DATA0;
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/* wtite data word to DATA register */
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*(pdata + data_reg) = (uint32_t)data;
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}
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/*!
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\brief SLCD data update request
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\param[in] none
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\param[out] none
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\retval none
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*/
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void slcd_data_update_request(void)
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{
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SLCD_STAT |= SLCD_STAT_UPRF;
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}
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/*!
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\brief enable SLCD interface
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\param[in] none
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\param[out] none
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\retval none
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*/
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void slcd_enable(void)
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{
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SLCD_CTL |= SLCD_CTL_LCDON;
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}
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/*!
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\brief disable SLCD interface
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\param[in] none
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\param[out] none
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\retval none
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*/
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void slcd_disable(void)
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{
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SLCD_CTL &= ~(SLCD_CTL_LCDON);
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}
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#endif /* GD32F170_190 */
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