mirror of
https://github.com/EFeru/hoverboard-sideboard-hack-GD.git
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237 lines
15 KiB
C
237 lines
15 KiB
C
/*!
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\file gd32f1x0.h
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\brief general definitions for gd32f1x0
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*/
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/*
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Copyright (C) 2017 GigaDevice
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2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
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2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
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2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
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2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
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*/
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#ifndef GD32F1X0_H
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#define GD32F1X0_H
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#ifdef cplusplus
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extern "C" {
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#endif
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/* define GD32F1x0 */
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#if !defined (GD32F1x0)
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#define GD32F1x0
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#endif /* define GD32F1x0 */
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#if !defined (GD32F1x0)
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#error "Please select the target GD32F1x0 device used in your application (in gd32f1x0.h file)"
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#endif /* undefine GD32F1x0 tip */
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/* define GD32F1x0 device category */
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#if (!defined (GD32F170_190))&&(!defined (GD32F130_150))
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#error "Please select GD32F1x0 device category( GD32F130_150 or GD32F170_190 )"
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#endif /* undefine GD32F170_190 or GD32F130_150 tip */
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#if (defined (GD32F170_190))&&(defined (GD32F130_150))
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#error "Please select one GD32F1x0 device category( GD32F130_150 or GD32F170_190 )"
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#endif /* define GD32F170_190 and GD32F130_150 tip */
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/* define value of high speed crystal oscillator (HXTAL) in Hz */
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#if !defined (HXTAL_VALUE)
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#define HXTAL_VALUE ((uint32_t)8000000)
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#endif /* high speed crystal oscillator value */
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/* define startup timeout value of high speed crystal oscillator (HXTAL) */
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#if !defined (HXTAL_STARTUP_TIMEOUT)
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#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800)
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#endif /* high speed crystal oscillator startup timeout */
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/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
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#if !defined (IRC8M_VALUE)
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#define IRC8M_VALUE ((uint32_t)8000000)
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#endif /* internal 8MHz RC oscillator value */
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/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
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#if !defined (IRC8M_STARTUP_TIMEOUT)
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#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
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#endif /* internal 8MHz RC oscillator startup timeout */
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/* define value of internal RC oscillator for ADC in Hz */
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#ifdef GD32F170_190
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#if !defined (IRC28M_VALUE)
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#define IRC28M_VALUE ((uint32_t)28000000)
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#endif /* IRC28M for GD32F170_190 */
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#else
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#if !defined (IRC14M_VALUE)
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#define IRC14M_VALUE ((uint32_t)14000000)
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#endif /* IRC14M for GD32F130_150 */
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#endif /* GD32F170_190 */
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/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
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#if !defined (IRC40K_VALUE)
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#define IRC40K_VALUE ((uint32_t)40000)
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#endif /* internal 40KHz RC oscillator value */
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/* define value of low speed crystal oscillator (LXTAL)in Hz */
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#if !defined (LXTAL_VALUE)
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#define LXTAL_VALUE ((uint32_t)32768)
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#endif /* low speed crystal oscillator value */
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/* GD32F1x0 firmware library version number V3.0 */
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#define __GD32F1x0_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
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#define __GD32F1x0_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
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#define __GD32F1x0_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __GD32F1x0_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __GD32F1x0_STDPERIPH_VERSION ((__GD32F1x0_STDPERIPH_VERSION_MAIN << 24)\
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|(__GD32F1x0_STDPERIPH_VERSION_SUB1 << 16)\
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|(__GD32F1x0_STDPERIPH_VERSION_SUB2 << 8)\
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|(__GD32F1x0_STDPERIPH_VERSION_RC))
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/* configuration of the Cortex-M3 processor and core peripherals */
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#define __MPU_PRESENT 1 /*!< GD32F1x0 do not provide MPU */
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#define __NVIC_PRIO_BITS 4 /*!< GD32F1x0 uses 4 bits for the priority levels */
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#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
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/* define interrupt number */
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typedef enum IRQn
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{
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/* Cortex-M3 processor exceptions numbers */
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NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 memory management interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M3 bus fault interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M3 usage fault interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV call interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 debug monitor interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M3 pend SV interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M3 system tick interrupt */
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/* interruput numbers */
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WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
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LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
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RTC_IRQn = 2, /*!< RTC through EXTI line interrupt */
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FMC_IRQn = 3, /*!< FMC interrupt */
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RCU_IRQn = 4, /*!< RCU interrupt */
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EXTI0_1_IRQn = 5, /*!< EXTI line 0 and 1 interrupts */
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EXTI2_3_IRQn = 6, /*!< EXTI line 2 and 3 interrupts */
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EXTI4_15_IRQn = 7, /*!< EXTI line 4 to 15 interrupts */
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TSI_IRQn = 8, /*!< TSI Interrupt */
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DMA_Channel0_IRQn = 9, /*!< DMA channel 0 interrupt */
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DMA_Channel1_2_IRQn = 10, /*!< DMA channel 1 and channel 2 interrupts */
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DMA_Channel3_4_IRQn = 11, /*!< DMA channel 3 and channel 4 interrupts */
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ADC_CMP_IRQn = 12, /*!< ADC, CMP0 and CMP1 interrupts */
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TIMER0_BRK_UP_TRG_COM_IRQn = 13, /*!< TIMER0 break, update, trigger and commutation interrupts */
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TIMER0_Channel_IRQn = 14, /*!< TIMER0 channel interrupt */
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TIMER1_IRQn = 15, /*!< TIMER1 interrupt */
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TIMER2_IRQn = 16, /*!< TIMER2 interrupt */
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TIMER5_DAC_IRQn = 17, /*!< TIMER5 and DAC interrupts */
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TIMER13_IRQn = 19, /*!< TIMER13 interrupt */
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TIMER14_IRQn = 20, /*!< TIMER14 interrupt */
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TIMER15_IRQn = 21, /*!< TIMER15 interrupt */
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TIMER16_IRQn = 22, /*!< TIMER16 interrupt */
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I2C0_EV_IRQn = 23, /*!< I2C0 event interrupt */
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I2C1_EV_IRQn = 24, /*!< I2C1 event interrupt */
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SPI0_IRQn = 25, /*!< SPI0 interrupt */
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SPI1_IRQn = 26, /*!< SPI1 interrupt */
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USART0_IRQn = 27, /*!< USART0 interrupt */
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USART1_IRQn = 28, /*!< USART1 interrupt */
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CEC_IRQn = 30, /*!< CEC interrupt */
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I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
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I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
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I2C2_EV_IRQn = 35, /*!< I2C2 event interrupt */
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I2C2_ER_IRQn = 36, /*!< I2C2 error interrupt */
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USBD_LP_IRQn = 37, /*!< USBD_LP interrupt */
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USBD_HP_IRQn = 38, /*!< USBD_HP interrupt */
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USBDWakeUp_IRQChannel = 42, /*!< USBD_WKUP interrupt */
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CAN0_TX_IRQn = 43, /*!< CAN0 TX interrupt */
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CAN0_RX0_IRQn = 44, /*!< CAN0 RX0 interrupt */
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CAN0_RX1_IRQn = 45, /*!< CAN0 RX1 interrupt */
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CAN0_SCE_IRQn = 46, /*!< CAN0 SCE interrupt */
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SLCD_IRQn = 47, /*!< SLCD interrupt */
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DMA_Channel5_6_IRQn = 48, /*!< DMA1 channel 5 and channel 6 interrupts */
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SPI2_IRQn = 51, /*!< SPI2 global interrupt */
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CAN1_TX_IRQn = 70, /*!< CAN1 TX interrupt */
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CAN1_RX0_IRQn = 71, /*!< CAN1 RX0 interrupt */
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CAN1_RX1_IRQn = 72, /*!< CAN1 RX1 interrupt */
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CAN1_SCE_IRQn = 73, /*!< CAN1 SCE interrupt */
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} IRQn_Type;
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/* includes */
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#include "core_cm3.h"
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#include "system_gd32f1x0.h"
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#include <stdint.h>
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/* enum definitions */
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typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
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typedef enum {FALSE = 0, TRUE = !FALSE} bool;
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typedef enum {RESET = 0, SET = !RESET} FlagStatus;
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typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
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/* bit operations */
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#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
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#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
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#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
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#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
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#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
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#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
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/* main flash and SRAM memory map */
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#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
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#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */
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/* SRAM and peripheral base bit-band region */
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#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */
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#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */
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/* peripheral memory map */
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#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
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#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
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#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
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#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */
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/* advanced peripheral bus 1 memory map */
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#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
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#define SLCD_BASE (APB1_BUS_BASE + 0x00002400U) /*!< SLCD base address */
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#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
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#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
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#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
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#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
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#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
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#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
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#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */
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#define USBD_RAM_BASE (APB1_BUS_BASE + 0x00006000U) /*!< USBD RAM base address */
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#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
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#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
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#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
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#define CEC_BASE (APB1_BUS_BASE + 0x00007800U) /*!< CEC base address */
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#define OPA_BASE (APB1_BUS_BASE + 0x00007C5CU) /*!< OPA base address */
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#define IVREF_BASE (APB1_BUS_BASE + 0x00007C00U) /*!< IVREF base address */
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/* advanced peripheral bus 2 memory map */
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#define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */
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#define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */
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#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
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#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
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/* advanced high performance bus 1 memory map */
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#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */
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#define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */
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#define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */
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#define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */
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#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
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#define TSI_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< TSI base address */
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/* advanced high performance bus 2 memory map */
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#define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */
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/* option byte and debug memory map */
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#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
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#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
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/* define marco USE_STDPERIPH_DRIVER */
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#if !defined USE_STDPERIPH_DRIVER
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#define USE_STDPERIPH_DRIVER
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#endif
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#ifdef USE_STDPERIPH_DRIVER
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#include "gd32f1x0_libopt.h"
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#endif /* USE_STDPERIPH_DRIVER */
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#ifdef cplusplus
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}
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#endif
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#endif
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